Struct esp32::dport::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub pro_boot_remap_ctrl: Reg<PRO_BOOT_REMAP_CTRL_SPEC>,
    pub app_boot_remap_ctrl: Reg<APP_BOOT_REMAP_CTRL_SPEC>,
    pub access_check: Reg<ACCESS_CHECK_SPEC>,
    pub pro_dport_apb_mask0: Reg<PRO_DPORT_APB_MASK0_SPEC>,
    pub pro_dport_apb_mask1: Reg<PRO_DPORT_APB_MASK1_SPEC>,
    pub app_dport_apb_mask0: Reg<APP_DPORT_APB_MASK0_SPEC>,
    pub app_dport_apb_mask1: Reg<APP_DPORT_APB_MASK1_SPEC>,
    pub peri_clk_en: Reg<PERI_CLK_EN_SPEC>,
    pub peri_rst_en: Reg<PERI_RST_EN_SPEC>,
    pub wifi_bb_cfg: Reg<WIFI_BB_CFG_SPEC>,
    pub wifi_bb_cfg_2: Reg<WIFI_BB_CFG_2_SPEC>,
    pub appcpu_ctrl_a: Reg<APPCPU_CTRL_A_SPEC>,
    pub appcpu_ctrl_b: Reg<APPCPU_CTRL_B_SPEC>,
    pub appcpu_ctrl_c: Reg<APPCPU_CTRL_C_SPEC>,
    pub appcpu_ctrl_d: Reg<APPCPU_CTRL_D_SPEC>,
    pub cpu_per_conf: Reg<CPU_PER_CONF_SPEC>,
    pub pro_cache_ctrl: Reg<PRO_CACHE_CTRL_SPEC>,
    pub pro_cache_ctrl1: Reg<PRO_CACHE_CTRL1_SPEC>,
    pub pro_cache_lock_0_addr: Reg<PRO_CACHE_LOCK_0_ADDR_SPEC>,
    pub pro_cache_lock_1_addr: Reg<PRO_CACHE_LOCK_1_ADDR_SPEC>,
    pub pro_cache_lock_2_addr: Reg<PRO_CACHE_LOCK_2_ADDR_SPEC>,
    pub pro_cache_lock_3_addr: Reg<PRO_CACHE_LOCK_3_ADDR_SPEC>,
    pub app_cache_ctrl: Reg<APP_CACHE_CTRL_SPEC>,
    pub app_cache_ctrl1: Reg<APP_CACHE_CTRL1_SPEC>,
    pub app_cache_lock_0_addr: Reg<APP_CACHE_LOCK_0_ADDR_SPEC>,
    pub app_cache_lock_1_addr: Reg<APP_CACHE_LOCK_1_ADDR_SPEC>,
    pub app_cache_lock_2_addr: Reg<APP_CACHE_LOCK_2_ADDR_SPEC>,
    pub app_cache_lock_3_addr: Reg<APP_CACHE_LOCK_3_ADDR_SPEC>,
    pub tracemem_mux_mode: Reg<TRACEMEM_MUX_MODE_SPEC>,
    pub pro_tracemem_ena: Reg<PRO_TRACEMEM_ENA_SPEC>,
    pub app_tracemem_ena: Reg<APP_TRACEMEM_ENA_SPEC>,
    pub cache_mux_mode: Reg<CACHE_MUX_MODE_SPEC>,
    pub immu_page_mode: Reg<IMMU_PAGE_MODE_SPEC>,
    pub dmmu_page_mode: Reg<DMMU_PAGE_MODE_SPEC>,
    pub rom_mpu_ena: Reg<ROM_MPU_ENA_SPEC>,
    pub mem_pd_mask: Reg<MEM_PD_MASK_SPEC>,
    pub rom_pd_ctrl: Reg<ROM_PD_CTRL_SPEC>,
    pub rom_fo_ctrl: Reg<ROM_FO_CTRL_SPEC>,
    pub sram_pd_ctrl_0: Reg<SRAM_PD_CTRL_0_SPEC>,
    pub sram_pd_ctrl_1: Reg<SRAM_PD_CTRL_1_SPEC>,
    pub sram_fo_ctrl_0: Reg<SRAM_FO_CTRL_0_SPEC>,
    pub sram_fo_ctrl_1: Reg<SRAM_FO_CTRL_1_SPEC>,
    pub iram_dram_ahb_sel: Reg<IRAM_DRAM_AHB_SEL_SPEC>,
    pub tag_fo_ctrl: Reg<TAG_FO_CTRL_SPEC>,
    pub ahb_lite_mask: Reg<AHB_LITE_MASK_SPEC>,
    pub ahb_mpu_table_0: Reg<AHB_MPU_TABLE_0_SPEC>,
    pub ahb_mpu_table_1: Reg<AHB_MPU_TABLE_1_SPEC>,
    pub host_inf_sel: Reg<HOST_INF_SEL_SPEC>,
    pub perip_clk_en: Reg<PERIP_CLK_EN_SPEC>,
    pub perip_rst_en: Reg<PERIP_RST_EN_SPEC>,
    pub wifi_clk_en: Reg<WIFI_CLK_EN_SPEC>,
    pub core_rst_en: Reg<CORE_RST_EN_SPEC>,
    pub bt_lpck_div_int: Reg<BT_LPCK_DIV_INT_SPEC>,
    pub bt_lpck_div_frac: Reg<BT_LPCK_DIV_FRAC_SPEC>,
    pub cpu_intr_from_cpu_0: Reg<CPU_INTR_FROM_CPU_0_SPEC>,
    pub cpu_intr_from_cpu_1: Reg<CPU_INTR_FROM_CPU_1_SPEC>,
    pub cpu_intr_from_cpu_2: Reg<CPU_INTR_FROM_CPU_2_SPEC>,
    pub cpu_intr_from_cpu_3: Reg<CPU_INTR_FROM_CPU_3_SPEC>,
    pub pro_intr_status_0: Reg<PRO_INTR_STATUS_0_SPEC>,
    pub pro_intr_status_1: Reg<PRO_INTR_STATUS_1_SPEC>,
    pub pro_intr_status_2: Reg<PRO_INTR_STATUS_2_SPEC>,
    pub app_intr_status_0: Reg<APP_INTR_STATUS_0_SPEC>,
    pub app_intr_status_1: Reg<APP_INTR_STATUS_1_SPEC>,
    pub app_intr_status_2: Reg<APP_INTR_STATUS_2_SPEC>,
    pub pro_mac_intr_map: Reg<PRO_MAC_INTR_MAP_SPEC>,
    pub pro_mac_nmi_map: Reg<PRO_MAC_NMI_MAP_SPEC>,
    pub pro_bb_int_map: Reg<PRO_BB_INT_MAP_SPEC>,
    pub pro_bt_mac_int_map: Reg<PRO_BT_MAC_INT_MAP_SPEC>,
    pub pro_bt_bb_int_map: Reg<PRO_BT_BB_INT_MAP_SPEC>,
    pub pro_bt_bb_nmi_map: Reg<PRO_BT_BB_NMI_MAP_SPEC>,
    pub pro_rwbt_irq_map: Reg<PRO_RWBT_IRQ_MAP_SPEC>,
    pub pro_rwble_irq_map: Reg<PRO_RWBLE_IRQ_MAP_SPEC>,
    pub pro_rwbt_nmi_map: Reg<PRO_RWBT_NMI_MAP_SPEC>,
    pub pro_rwble_nmi_map: Reg<PRO_RWBLE_NMI_MAP_SPEC>,
    pub pro_slc0_intr_map: Reg<PRO_SLC0_INTR_MAP_SPEC>,
    pub pro_slc1_intr_map: Reg<PRO_SLC1_INTR_MAP_SPEC>,
    pub pro_uhci0_intr_map: Reg<PRO_UHCI0_INTR_MAP_SPEC>,
    pub pro_uhci1_intr_map: Reg<PRO_UHCI1_INTR_MAP_SPEC>,
    pub pro_tg_t0_level_int_map: Reg<PRO_TG_T0_LEVEL_INT_MAP_SPEC>,
    pub pro_tg_t1_level_int_map: Reg<PRO_TG_T1_LEVEL_INT_MAP_SPEC>,
    pub pro_tg_wdt_level_int_map: Reg<PRO_TG_WDT_LEVEL_INT_MAP_SPEC>,
    pub pro_tg_lact_level_int_map: Reg<PRO_TG_LACT_LEVEL_INT_MAP_SPEC>,
    pub pro_tg1_t0_level_int_map: Reg<PRO_TG1_T0_LEVEL_INT_MAP_SPEC>,
    pub pro_tg1_t1_level_int_map: Reg<PRO_TG1_T1_LEVEL_INT_MAP_SPEC>,
    pub pro_tg1_wdt_level_int_map: Reg<PRO_TG1_WDT_LEVEL_INT_MAP_SPEC>,
    pub pro_tg1_lact_level_int_map: Reg<PRO_TG1_LACT_LEVEL_INT_MAP_SPEC>,
    pub pro_gpio_interrupt_map: Reg<PRO_GPIO_INTERRUPT_MAP_SPEC>,
    pub pro_gpio_interrupt_nmi_map: Reg<PRO_GPIO_INTERRUPT_NMI_MAP_SPEC>,
    pub pro_cpu_intr_from_cpu_0_map: Reg<PRO_CPU_INTR_FROM_CPU_0_MAP_SPEC>,
    pub pro_cpu_intr_from_cpu_1_map: Reg<PRO_CPU_INTR_FROM_CPU_1_MAP_SPEC>,
    pub pro_cpu_intr_from_cpu_2_map: Reg<PRO_CPU_INTR_FROM_CPU_2_MAP_SPEC>,
    pub pro_cpu_intr_from_cpu_3_map: Reg<PRO_CPU_INTR_FROM_CPU_3_MAP_SPEC>,
    pub pro_spi_intr_0_map: Reg<PRO_SPI_INTR_0_MAP_SPEC>,
    pub pro_spi_intr_1_map: Reg<PRO_SPI_INTR_1_MAP_SPEC>,
    pub pro_spi_intr_2_map: Reg<PRO_SPI_INTR_2_MAP_SPEC>,
    pub pro_spi_intr_3_map: Reg<PRO_SPI_INTR_3_MAP_SPEC>,
    pub pro_i2s0_int_map: Reg<PRO_I2S0_INT_MAP_SPEC>,
    pub pro_i2s1_int_map: Reg<PRO_I2S1_INT_MAP_SPEC>,
    pub pro_uart_intr_map: Reg<PRO_UART_INTR_MAP_SPEC>,
    pub pro_uart1_intr_map: Reg<PRO_UART1_INTR_MAP_SPEC>,
    pub pro_uart2_intr_map: Reg<PRO_UART2_INTR_MAP_SPEC>,
    pub pro_sdio_host_interrupt_map: Reg<PRO_SDIO_HOST_INTERRUPT_MAP_SPEC>,
    pub pro_emac_int_map: Reg<PRO_EMAC_INT_MAP_SPEC>,
    pub pro_pwm0_intr_map: Reg<PRO_PWM0_INTR_MAP_SPEC>,
    pub pro_pwm1_intr_map: Reg<PRO_PWM1_INTR_MAP_SPEC>,
    pub pro_pwm2_intr_map: Reg<PRO_PWM2_INTR_MAP_SPEC>,
    pub pro_pwm3_intr_map: Reg<PRO_PWM3_INTR_MAP_SPEC>,
    pub pro_ledc_int_map: Reg<PRO_LEDC_INT_MAP_SPEC>,
    pub pro_efuse_int_map: Reg<PRO_EFUSE_INT_MAP_SPEC>,
    pub pro_can_int_map: Reg<PRO_CAN_INT_MAP_SPEC>,
    pub pro_rtc_core_intr_map: Reg<PRO_RTC_CORE_INTR_MAP_SPEC>,
    pub pro_rmt_intr_map: Reg<PRO_RMT_INTR_MAP_SPEC>,
    pub pro_pcnt_intr_map: Reg<PRO_PCNT_INTR_MAP_SPEC>,
    pub pro_i2c_ext0_intr_map: Reg<PRO_I2C_EXT0_INTR_MAP_SPEC>,
    pub pro_i2c_ext1_intr_map: Reg<PRO_I2C_EXT1_INTR_MAP_SPEC>,
    pub pro_rsa_intr_map: Reg<PRO_RSA_INTR_MAP_SPEC>,
    pub pro_spi1_dma_int_map: Reg<PRO_SPI1_DMA_INT_MAP_SPEC>,
    pub pro_spi2_dma_int_map: Reg<PRO_SPI2_DMA_INT_MAP_SPEC>,
    pub pro_spi3_dma_int_map: Reg<PRO_SPI3_DMA_INT_MAP_SPEC>,
    pub pro_wdg_int_map: Reg<PRO_WDG_INT_MAP_SPEC>,
    pub pro_timer_int1_map: Reg<PRO_TIMER_INT1_MAP_SPEC>,
    pub pro_timer_int2_map: Reg<PRO_TIMER_INT2_MAP_SPEC>,
    pub pro_tg_t0_edge_int_map: Reg<PRO_TG_T0_EDGE_INT_MAP_SPEC>,
    pub pro_tg_t1_edge_int_map: Reg<PRO_TG_T1_EDGE_INT_MAP_SPEC>,
    pub pro_tg_wdt_edge_int_map: Reg<PRO_TG_WDT_EDGE_INT_MAP_SPEC>,
    pub pro_tg_lact_edge_int_map: Reg<PRO_TG_LACT_EDGE_INT_MAP_SPEC>,
    pub pro_tg1_t0_edge_int_map: Reg<PRO_TG1_T0_EDGE_INT_MAP_SPEC>,
    pub pro_tg1_t1_edge_int_map: Reg<PRO_TG1_T1_EDGE_INT_MAP_SPEC>,
    pub pro_tg1_wdt_edge_int_map: Reg<PRO_TG1_WDT_EDGE_INT_MAP_SPEC>,
    pub pro_tg1_lact_edge_int_map: Reg<PRO_TG1_LACT_EDGE_INT_MAP_SPEC>,
    pub pro_mmu_ia_int_map: Reg<PRO_MMU_IA_INT_MAP_SPEC>,
    pub pro_mpu_ia_int_map: Reg<PRO_MPU_IA_INT_MAP_SPEC>,
    pub pro_cache_ia_int_map: Reg<PRO_CACHE_IA_INT_MAP_SPEC>,
    pub app_mac_intr_map: Reg<APP_MAC_INTR_MAP_SPEC>,
    pub app_mac_nmi_map: Reg<APP_MAC_NMI_MAP_SPEC>,
    pub app_bb_int_map: Reg<APP_BB_INT_MAP_SPEC>,
    pub app_bt_mac_int_map: Reg<APP_BT_MAC_INT_MAP_SPEC>,
    pub app_bt_bb_int_map: Reg<APP_BT_BB_INT_MAP_SPEC>,
    pub app_bt_bb_nmi_map: Reg<APP_BT_BB_NMI_MAP_SPEC>,
    pub app_rwbt_irq_map: Reg<APP_RWBT_IRQ_MAP_SPEC>,
    pub app_rwble_irq_map: Reg<APP_RWBLE_IRQ_MAP_SPEC>,
    pub app_rwbt_nmi_map: Reg<APP_RWBT_NMI_MAP_SPEC>,
    pub app_rwble_nmi_map: Reg<APP_RWBLE_NMI_MAP_SPEC>,
    pub app_slc0_intr_map: Reg<APP_SLC0_INTR_MAP_SPEC>,
    pub app_slc1_intr_map: Reg<APP_SLC1_INTR_MAP_SPEC>,
    pub app_uhci0_intr_map: Reg<APP_UHCI0_INTR_MAP_SPEC>,
    pub app_uhci1_intr_map: Reg<APP_UHCI1_INTR_MAP_SPEC>,
    pub app_tg_t0_level_int_map: Reg<APP_TG_T0_LEVEL_INT_MAP_SPEC>,
    pub app_tg_t1_level_int_map: Reg<APP_TG_T1_LEVEL_INT_MAP_SPEC>,
    pub app_tg_wdt_level_int_map: Reg<APP_TG_WDT_LEVEL_INT_MAP_SPEC>,
    pub app_tg_lact_level_int_map: Reg<APP_TG_LACT_LEVEL_INT_MAP_SPEC>,
    pub app_tg1_t0_level_int_map: Reg<APP_TG1_T0_LEVEL_INT_MAP_SPEC>,
    pub app_tg1_t1_level_int_map: Reg<APP_TG1_T1_LEVEL_INT_MAP_SPEC>,
    pub app_tg1_wdt_level_int_map: Reg<APP_TG1_WDT_LEVEL_INT_MAP_SPEC>,
    pub app_tg1_lact_level_int_map: Reg<APP_TG1_LACT_LEVEL_INT_MAP_SPEC>,
    pub app_gpio_interrupt_map: Reg<APP_GPIO_INTERRUPT_MAP_SPEC>,
    pub app_gpio_interrupt_nmi_map: Reg<APP_GPIO_INTERRUPT_NMI_MAP_SPEC>,
    pub app_cpu_intr_from_cpu_0_map: Reg<APP_CPU_INTR_FROM_CPU_0_MAP_SPEC>,
    pub app_cpu_intr_from_cpu_1_map: Reg<APP_CPU_INTR_FROM_CPU_1_MAP_SPEC>,
    pub app_cpu_intr_from_cpu_2_map: Reg<APP_CPU_INTR_FROM_CPU_2_MAP_SPEC>,
    pub app_cpu_intr_from_cpu_3_map: Reg<APP_CPU_INTR_FROM_CPU_3_MAP_SPEC>,
    pub app_spi_intr_0_map: Reg<APP_SPI_INTR_0_MAP_SPEC>,
    pub app_spi_intr_1_map: Reg<APP_SPI_INTR_1_MAP_SPEC>,
    pub app_spi_intr_2_map: Reg<APP_SPI_INTR_2_MAP_SPEC>,
    pub app_spi_intr_3_map: Reg<APP_SPI_INTR_3_MAP_SPEC>,
    pub app_i2s0_int_map: Reg<APP_I2S0_INT_MAP_SPEC>,
    pub app_i2s1_int_map: Reg<APP_I2S1_INT_MAP_SPEC>,
    pub app_uart_intr_map: Reg<APP_UART_INTR_MAP_SPEC>,
    pub app_uart1_intr_map: Reg<APP_UART1_INTR_MAP_SPEC>,
    pub app_uart2_intr_map: Reg<APP_UART2_INTR_MAP_SPEC>,
    pub app_sdio_host_interrupt_map: Reg<APP_SDIO_HOST_INTERRUPT_MAP_SPEC>,
    pub app_emac_int_map: Reg<APP_EMAC_INT_MAP_SPEC>,
    pub app_pwm0_intr_map: Reg<APP_PWM0_INTR_MAP_SPEC>,
    pub app_pwm1_intr_map: Reg<APP_PWM1_INTR_MAP_SPEC>,
    pub app_pwm2_intr_map: Reg<APP_PWM2_INTR_MAP_SPEC>,
    pub app_pwm3_intr_map: Reg<APP_PWM3_INTR_MAP_SPEC>,
    pub app_ledc_int_map: Reg<APP_LEDC_INT_MAP_SPEC>,
    pub app_efuse_int_map: Reg<APP_EFUSE_INT_MAP_SPEC>,
    pub app_can_int_map: Reg<APP_CAN_INT_MAP_SPEC>,
    pub app_rtc_core_intr_map: Reg<APP_RTC_CORE_INTR_MAP_SPEC>,
    pub app_rmt_intr_map: Reg<APP_RMT_INTR_MAP_SPEC>,
    pub app_pcnt_intr_map: Reg<APP_PCNT_INTR_MAP_SPEC>,
    pub app_i2c_ext0_intr_map: Reg<APP_I2C_EXT0_INTR_MAP_SPEC>,
    pub app_i2c_ext1_intr_map: Reg<APP_I2C_EXT1_INTR_MAP_SPEC>,
    pub app_rsa_intr_map: Reg<APP_RSA_INTR_MAP_SPEC>,
    pub app_spi1_dma_int_map: Reg<APP_SPI1_DMA_INT_MAP_SPEC>,
    pub app_spi2_dma_int_map: Reg<APP_SPI2_DMA_INT_MAP_SPEC>,
    pub app_spi3_dma_int_map: Reg<APP_SPI3_DMA_INT_MAP_SPEC>,
    pub app_wdg_int_map: Reg<APP_WDG_INT_MAP_SPEC>,
    pub app_timer_int1_map: Reg<APP_TIMER_INT1_MAP_SPEC>,
    pub app_timer_int2_map: Reg<APP_TIMER_INT2_MAP_SPEC>,
    pub app_tg_t0_edge_int_map: Reg<APP_TG_T0_EDGE_INT_MAP_SPEC>,
    pub app_tg_t1_edge_int_map: Reg<APP_TG_T1_EDGE_INT_MAP_SPEC>,
    pub app_tg_wdt_edge_int_map: Reg<APP_TG_WDT_EDGE_INT_MAP_SPEC>,
    pub app_tg_lact_edge_int_map: Reg<APP_TG_LACT_EDGE_INT_MAP_SPEC>,
    pub app_tg1_t0_edge_int_map: Reg<APP_TG1_T0_EDGE_INT_MAP_SPEC>,
    pub app_tg1_t1_edge_int_map: Reg<APP_TG1_T1_EDGE_INT_MAP_SPEC>,
    pub app_tg1_wdt_edge_int_map: Reg<APP_TG1_WDT_EDGE_INT_MAP_SPEC>,
    pub app_tg1_lact_edge_int_map: Reg<APP_TG1_LACT_EDGE_INT_MAP_SPEC>,
    pub app_mmu_ia_int_map: Reg<APP_MMU_IA_INT_MAP_SPEC>,
    pub app_mpu_ia_int_map: Reg<APP_MPU_IA_INT_MAP_SPEC>,
    pub app_cache_ia_int_map: Reg<APP_CACHE_IA_INT_MAP_SPEC>,
    pub ahblite_mpu_table_uart: Reg<AHBLITE_MPU_TABLE_UART_SPEC>,
    pub ahblite_mpu_table_spi1: Reg<AHBLITE_MPU_TABLE_SPI1_SPEC>,
    pub ahblite_mpu_table_spi0: Reg<AHBLITE_MPU_TABLE_SPI0_SPEC>,
    pub ahblite_mpu_table_gpio: Reg<AHBLITE_MPU_TABLE_GPIO_SPEC>,
    pub ahblite_mpu_table_fe2: Reg<AHBLITE_MPU_TABLE_FE2_SPEC>,
    pub ahblite_mpu_table_fe: Reg<AHBLITE_MPU_TABLE_FE_SPEC>,
    pub ahblite_mpu_table_timer: Reg<AHBLITE_MPU_TABLE_TIMER_SPEC>,
    pub ahblite_mpu_table_rtc: Reg<AHBLITE_MPU_TABLE_RTC_SPEC>,
    pub ahblite_mpu_table_io_mux: Reg<AHBLITE_MPU_TABLE_IO_MUX_SPEC>,
    pub ahblite_mpu_table_wdg: Reg<AHBLITE_MPU_TABLE_WDG_SPEC>,
    pub ahblite_mpu_table_hinf: Reg<AHBLITE_MPU_TABLE_HINF_SPEC>,
    pub ahblite_mpu_table_uhci1: Reg<AHBLITE_MPU_TABLE_UHCI1_SPEC>,
    pub ahblite_mpu_table_misc: Reg<AHBLITE_MPU_TABLE_MISC_SPEC>,
    pub ahblite_mpu_table_i2c: Reg<AHBLITE_MPU_TABLE_I2C_SPEC>,
    pub ahblite_mpu_table_i2s0: Reg<AHBLITE_MPU_TABLE_I2S0_SPEC>,
    pub ahblite_mpu_table_uart1: Reg<AHBLITE_MPU_TABLE_UART1_SPEC>,
    pub ahblite_mpu_table_bt: Reg<AHBLITE_MPU_TABLE_BT_SPEC>,
    pub ahblite_mpu_table_bt_buffer: Reg<AHBLITE_MPU_TABLE_BT_BUFFER_SPEC>,
    pub ahblite_mpu_table_i2c_ext0: Reg<AHBLITE_MPU_TABLE_I2C_EXT0_SPEC>,
    pub ahblite_mpu_table_uhci0: Reg<AHBLITE_MPU_TABLE_UHCI0_SPEC>,
    pub ahblite_mpu_table_slchost: Reg<AHBLITE_MPU_TABLE_SLCHOST_SPEC>,
    pub ahblite_mpu_table_rmt: Reg<AHBLITE_MPU_TABLE_RMT_SPEC>,
    pub ahblite_mpu_table_pcnt: Reg<AHBLITE_MPU_TABLE_PCNT_SPEC>,
    pub ahblite_mpu_table_slc: Reg<AHBLITE_MPU_TABLE_SLC_SPEC>,
    pub ahblite_mpu_table_ledc: Reg<AHBLITE_MPU_TABLE_LEDC_SPEC>,
    pub ahblite_mpu_table_efuse: Reg<AHBLITE_MPU_TABLE_EFUSE_SPEC>,
    pub ahblite_mpu_table_spi_encrypt: Reg<AHBLITE_MPU_TABLE_SPI_ENCRYPT_SPEC>,
    pub ahblite_mpu_table_bb: Reg<AHBLITE_MPU_TABLE_BB_SPEC>,
    pub ahblite_mpu_table_pwm0: Reg<AHBLITE_MPU_TABLE_PWM0_SPEC>,
    pub ahblite_mpu_table_timergroup: Reg<AHBLITE_MPU_TABLE_TIMERGROUP_SPEC>,
    pub ahblite_mpu_table_timergroup1: Reg<AHBLITE_MPU_TABLE_TIMERGROUP1_SPEC>,
    pub ahblite_mpu_table_spi2: Reg<AHBLITE_MPU_TABLE_SPI2_SPEC>,
    pub ahblite_mpu_table_spi3: Reg<AHBLITE_MPU_TABLE_SPI3_SPEC>,
    pub ahblite_mpu_table_apb_ctrl: Reg<AHBLITE_MPU_TABLE_APB_CTRL_SPEC>,
    pub ahblite_mpu_table_i2c_ext1: Reg<AHBLITE_MPU_TABLE_I2C_EXT1_SPEC>,
    pub ahblite_mpu_table_sdio_host: Reg<AHBLITE_MPU_TABLE_SDIO_HOST_SPEC>,
    pub ahblite_mpu_table_emac: Reg<AHBLITE_MPU_TABLE_EMAC_SPEC>,
    pub ahblite_mpu_table_can: Reg<AHBLITE_MPU_TABLE_CAN_SPEC>,
    pub ahblite_mpu_table_pwm1: Reg<AHBLITE_MPU_TABLE_PWM1_SPEC>,
    pub ahblite_mpu_table_i2s1: Reg<AHBLITE_MPU_TABLE_I2S1_SPEC>,
    pub ahblite_mpu_table_uart2: Reg<AHBLITE_MPU_TABLE_UART2_SPEC>,
    pub ahblite_mpu_table_pwm2: Reg<AHBLITE_MPU_TABLE_PWM2_SPEC>,
    pub ahblite_mpu_table_pwm3: Reg<AHBLITE_MPU_TABLE_PWM3_SPEC>,
    pub ahblite_mpu_table_rwbt: Reg<AHBLITE_MPU_TABLE_RWBT_SPEC>,
    pub ahblite_mpu_table_btmac: Reg<AHBLITE_MPU_TABLE_BTMAC_SPEC>,
    pub ahblite_mpu_table_wifimac: Reg<AHBLITE_MPU_TABLE_WIFIMAC_SPEC>,
    pub ahblite_mpu_table_pwr: Reg<AHBLITE_MPU_TABLE_PWR_SPEC>,
    pub mem_access_dbug0: Reg<MEM_ACCESS_DBUG0_SPEC>,
    pub mem_access_dbug1: Reg<MEM_ACCESS_DBUG1_SPEC>,
    pub pro_dcache_dbug0: Reg<PRO_DCACHE_DBUG0_SPEC>,
    pub pro_dcache_dbug1: Reg<PRO_DCACHE_DBUG1_SPEC>,
    pub pro_dcache_dbug2: Reg<PRO_DCACHE_DBUG2_SPEC>,
    pub pro_dcache_dbug3: Reg<PRO_DCACHE_DBUG3_SPEC>,
    pub pro_dcache_dbug4: Reg<PRO_DCACHE_DBUG4_SPEC>,
    pub pro_dcache_dbug5: Reg<PRO_DCACHE_DBUG5_SPEC>,
    pub pro_dcache_dbug6: Reg<PRO_DCACHE_DBUG6_SPEC>,
    pub pro_dcache_dbug7: Reg<PRO_DCACHE_DBUG7_SPEC>,
    pub pro_dcache_dbug8: Reg<PRO_DCACHE_DBUG8_SPEC>,
    pub pro_dcache_dbug9: Reg<PRO_DCACHE_DBUG9_SPEC>,
    pub app_dcache_dbug0: Reg<APP_DCACHE_DBUG0_SPEC>,
    pub app_dcache_dbug1: Reg<APP_DCACHE_DBUG1_SPEC>,
    pub app_dcache_dbug2: Reg<APP_DCACHE_DBUG2_SPEC>,
    pub app_dcache_dbug3: Reg<APP_DCACHE_DBUG3_SPEC>,
    pub app_dcache_dbug4: Reg<APP_DCACHE_DBUG4_SPEC>,
    pub app_dcache_dbug5: Reg<APP_DCACHE_DBUG5_SPEC>,
    pub app_dcache_dbug6: Reg<APP_DCACHE_DBUG6_SPEC>,
    pub app_dcache_dbug7: Reg<APP_DCACHE_DBUG7_SPEC>,
    pub app_dcache_dbug8: Reg<APP_DCACHE_DBUG8_SPEC>,
    pub app_dcache_dbug9: Reg<APP_DCACHE_DBUG9_SPEC>,
    pub pro_cpu_record_ctrl: Reg<PRO_CPU_RECORD_CTRL_SPEC>,
    pub pro_cpu_record_status: Reg<PRO_CPU_RECORD_STATUS_SPEC>,
    pub pro_cpu_record_pid: Reg<PRO_CPU_RECORD_PID_SPEC>,
    pub pro_cpu_record_pdebuginst: Reg<PRO_CPU_RECORD_PDEBUGINST_SPEC>,
    pub pro_cpu_record_pdebugstatus: Reg<PRO_CPU_RECORD_PDEBUGSTATUS_SPEC>,
    pub pro_cpu_record_pdebugdata: Reg<PRO_CPU_RECORD_PDEBUGDATA_SPEC>,
    pub pro_cpu_record_pdebugpc: Reg<PRO_CPU_RECORD_PDEBUGPC_SPEC>,
    pub pro_cpu_record_pdebugls0stat: Reg<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC>,
    pub pro_cpu_record_pdebugls0addr: Reg<PRO_CPU_RECORD_PDEBUGLS0ADDR_SPEC>,
    pub pro_cpu_record_pdebugls0data: Reg<PRO_CPU_RECORD_PDEBUGLS0DATA_SPEC>,
    pub app_cpu_record_ctrl: Reg<APP_CPU_RECORD_CTRL_SPEC>,
    pub app_cpu_record_status: Reg<APP_CPU_RECORD_STATUS_SPEC>,
    pub app_cpu_record_pid: Reg<APP_CPU_RECORD_PID_SPEC>,
    pub app_cpu_record_pdebuginst: Reg<APP_CPU_RECORD_PDEBUGINST_SPEC>,
    pub app_cpu_record_pdebugstatus: Reg<APP_CPU_RECORD_PDEBUGSTATUS_SPEC>,
    pub app_cpu_record_pdebugdata: Reg<APP_CPU_RECORD_PDEBUGDATA_SPEC>,
    pub app_cpu_record_pdebugpc: Reg<APP_CPU_RECORD_PDEBUGPC_SPEC>,
    pub app_cpu_record_pdebugls0stat: Reg<APP_CPU_RECORD_PDEBUGLS0STAT_SPEC>,
    pub app_cpu_record_pdebugls0addr: Reg<APP_CPU_RECORD_PDEBUGLS0ADDR_SPEC>,
    pub app_cpu_record_pdebugls0data: Reg<APP_CPU_RECORD_PDEBUGLS0DATA_SPEC>,
    pub rsa_pd_ctrl: Reg<RSA_PD_CTRL_SPEC>,
    pub rom_mpu_table0: Reg<ROM_MPU_TABLE0_SPEC>,
    pub rom_mpu_table1: Reg<ROM_MPU_TABLE1_SPEC>,
    pub rom_mpu_table2: Reg<ROM_MPU_TABLE2_SPEC>,
    pub rom_mpu_table3: Reg<ROM_MPU_TABLE3_SPEC>,
    pub shrom_mpu_table0: Reg<SHROM_MPU_TABLE0_SPEC>,
    pub shrom_mpu_table1: Reg<SHROM_MPU_TABLE1_SPEC>,
    pub shrom_mpu_table2: Reg<SHROM_MPU_TABLE2_SPEC>,
    pub shrom_mpu_table3: Reg<SHROM_MPU_TABLE3_SPEC>,
    pub shrom_mpu_table4: Reg<SHROM_MPU_TABLE4_SPEC>,
    pub shrom_mpu_table5: Reg<SHROM_MPU_TABLE5_SPEC>,
    pub shrom_mpu_table6: Reg<SHROM_MPU_TABLE6_SPEC>,
    pub shrom_mpu_table7: Reg<SHROM_MPU_TABLE7_SPEC>,
    pub shrom_mpu_table8: Reg<SHROM_MPU_TABLE8_SPEC>,
    pub shrom_mpu_table9: Reg<SHROM_MPU_TABLE9_SPEC>,
    pub shrom_mpu_table10: Reg<SHROM_MPU_TABLE10_SPEC>,
    pub shrom_mpu_table11: Reg<SHROM_MPU_TABLE11_SPEC>,
    pub shrom_mpu_table12: Reg<SHROM_MPU_TABLE12_SPEC>,
    pub shrom_mpu_table13: Reg<SHROM_MPU_TABLE13_SPEC>,
    pub shrom_mpu_table14: Reg<SHROM_MPU_TABLE14_SPEC>,
    pub shrom_mpu_table15: Reg<SHROM_MPU_TABLE15_SPEC>,
    pub shrom_mpu_table16: Reg<SHROM_MPU_TABLE16_SPEC>,
    pub shrom_mpu_table17: Reg<SHROM_MPU_TABLE17_SPEC>,
    pub shrom_mpu_table18: Reg<SHROM_MPU_TABLE18_SPEC>,
    pub shrom_mpu_table19: Reg<SHROM_MPU_TABLE19_SPEC>,
    pub shrom_mpu_table20: Reg<SHROM_MPU_TABLE20_SPEC>,
    pub shrom_mpu_table21: Reg<SHROM_MPU_TABLE21_SPEC>,
    pub shrom_mpu_table22: Reg<SHROM_MPU_TABLE22_SPEC>,
    pub shrom_mpu_table23: Reg<SHROM_MPU_TABLE23_SPEC>,
    pub immu_table0: Reg<IMMU_TABLE0_SPEC>,
    pub immu_table1: Reg<IMMU_TABLE1_SPEC>,
    pub immu_table2: Reg<IMMU_TABLE2_SPEC>,
    pub immu_table3: Reg<IMMU_TABLE3_SPEC>,
    pub immu_table4: Reg<IMMU_TABLE4_SPEC>,
    pub immu_table5: Reg<IMMU_TABLE5_SPEC>,
    pub immu_table6: Reg<IMMU_TABLE6_SPEC>,
    pub immu_table7: Reg<IMMU_TABLE7_SPEC>,
    pub immu_table8: Reg<IMMU_TABLE8_SPEC>,
    pub immu_table9: Reg<IMMU_TABLE9_SPEC>,
    pub immu_table10: Reg<IMMU_TABLE10_SPEC>,
    pub immu_table11: Reg<IMMU_TABLE11_SPEC>,
    pub immu_table12: Reg<IMMU_TABLE12_SPEC>,
    pub immu_table13: Reg<IMMU_TABLE13_SPEC>,
    pub immu_table14: Reg<IMMU_TABLE14_SPEC>,
    pub immu_table15: Reg<IMMU_TABLE15_SPEC>,
    pub dmmu_table0: Reg<DMMU_TABLE0_SPEC>,
    pub dmmu_table1: Reg<DMMU_TABLE1_SPEC>,
    pub dmmu_table2: Reg<DMMU_TABLE2_SPEC>,
    pub dmmu_table3: Reg<DMMU_TABLE3_SPEC>,
    pub dmmu_table4: Reg<DMMU_TABLE4_SPEC>,
    pub dmmu_table5: Reg<DMMU_TABLE5_SPEC>,
    pub dmmu_table6: Reg<DMMU_TABLE6_SPEC>,
    pub dmmu_table7: Reg<DMMU_TABLE7_SPEC>,
    pub dmmu_table8: Reg<DMMU_TABLE8_SPEC>,
    pub dmmu_table9: Reg<DMMU_TABLE9_SPEC>,
    pub dmmu_table10: Reg<DMMU_TABLE10_SPEC>,
    pub dmmu_table11: Reg<DMMU_TABLE11_SPEC>,
    pub dmmu_table12: Reg<DMMU_TABLE12_SPEC>,
    pub dmmu_table13: Reg<DMMU_TABLE13_SPEC>,
    pub dmmu_table14: Reg<DMMU_TABLE14_SPEC>,
    pub dmmu_table15: Reg<DMMU_TABLE15_SPEC>,
    pub pro_intrusion_ctrl: Reg<PRO_INTRUSION_CTRL_SPEC>,
    pub pro_intrusion_status: Reg<PRO_INTRUSION_STATUS_SPEC>,
    pub app_intrusion_ctrl: Reg<APP_INTRUSION_CTRL_SPEC>,
    pub app_intrusion_status: Reg<APP_INTRUSION_STATUS_SPEC>,
    pub front_end_mem_pd: Reg<FRONT_END_MEM_PD_SPEC>,
    pub mmu_ia_int_en: Reg<MMU_IA_INT_EN_SPEC>,
    pub mpu_ia_int_en: Reg<MPU_IA_INT_EN_SPEC>,
    pub cache_ia_int_en: Reg<CACHE_IA_INT_EN_SPEC>,
    pub secure_boot_ctrl: Reg<SECURE_BOOT_CTRL_SPEC>,
    pub spi_dma_chan_sel: Reg<SPI_DMA_CHAN_SEL_SPEC>,
    pub pro_vecbase_ctrl: Reg<PRO_VECBASE_CTRL_SPEC>,
    pub pro_vecbase_set: Reg<PRO_VECBASE_SET_SPEC>,
    pub app_vecbase_ctrl: Reg<APP_VECBASE_CTRL_SPEC>,
    pub app_vecbase_set: Reg<APP_VECBASE_SET_SPEC>,
    pub date: Reg<DATE_SPEC>,
    // some fields omitted
}

Register block

Fields

pro_boot_remap_ctrl: Reg<PRO_BOOT_REMAP_CTRL_SPEC>

0x00 - DPORT_PRO_BOOT_REMAP_CTRL

app_boot_remap_ctrl: Reg<APP_BOOT_REMAP_CTRL_SPEC>

0x04 - DPORT_APP_BOOT_REMAP_CTRL

access_check: Reg<ACCESS_CHECK_SPEC>

0x08 - DPORT_ACCESS_CHECK

pro_dport_apb_mask0: Reg<PRO_DPORT_APB_MASK0_SPEC>

0x0c - DPORT_PRO_DPORT_APB_MASK0

pro_dport_apb_mask1: Reg<PRO_DPORT_APB_MASK1_SPEC>

0x10 - DPORT_PRO_DPORT_APB_MASK1

app_dport_apb_mask0: Reg<APP_DPORT_APB_MASK0_SPEC>

0x14 - DPORT_APP_DPORT_APB_MASK0

app_dport_apb_mask1: Reg<APP_DPORT_APB_MASK1_SPEC>

0x18 - DPORT_APP_DPORT_APB_MASK1

peri_clk_en: Reg<PERI_CLK_EN_SPEC>

0x1c - DPORT_PERI_CLK_EN

peri_rst_en: Reg<PERI_RST_EN_SPEC>

0x20 - DPORT_PERI_RST_EN

wifi_bb_cfg: Reg<WIFI_BB_CFG_SPEC>

0x24 - DPORT_WIFI_BB_CFG

wifi_bb_cfg_2: Reg<WIFI_BB_CFG_2_SPEC>

0x28 - DPORT_WIFI_BB_CFG_2

appcpu_ctrl_a: Reg<APPCPU_CTRL_A_SPEC>

0x2c - DPORT_APPCPU_CTRL_A

appcpu_ctrl_b: Reg<APPCPU_CTRL_B_SPEC>

0x30 - DPORT_APPCPU_CTRL_B

appcpu_ctrl_c: Reg<APPCPU_CTRL_C_SPEC>

0x34 - DPORT_APPCPU_CTRL_C

appcpu_ctrl_d: Reg<APPCPU_CTRL_D_SPEC>

0x38 - DPORT_APPCPU_CTRL_D

cpu_per_conf: Reg<CPU_PER_CONF_SPEC>

0x3c - DPORT_CPU_PER_CONF

pro_cache_ctrl: Reg<PRO_CACHE_CTRL_SPEC>

0x40 - DPORT_PRO_CACHE_CTRL

pro_cache_ctrl1: Reg<PRO_CACHE_CTRL1_SPEC>

0x44 - DPORT_PRO_CACHE_CTRL1

pro_cache_lock_0_addr: Reg<PRO_CACHE_LOCK_0_ADDR_SPEC>

0x48 - DPORT_PRO_CACHE_LOCK_0_ADDR

pro_cache_lock_1_addr: Reg<PRO_CACHE_LOCK_1_ADDR_SPEC>

0x4c - DPORT_PRO_CACHE_LOCK_1_ADDR

pro_cache_lock_2_addr: Reg<PRO_CACHE_LOCK_2_ADDR_SPEC>

0x50 - DPORT_PRO_CACHE_LOCK_2_ADDR

pro_cache_lock_3_addr: Reg<PRO_CACHE_LOCK_3_ADDR_SPEC>

0x54 - DPORT_PRO_CACHE_LOCK_3_ADDR

app_cache_ctrl: Reg<APP_CACHE_CTRL_SPEC>

0x58 - DPORT_APP_CACHE_CTRL

app_cache_ctrl1: Reg<APP_CACHE_CTRL1_SPEC>

0x5c - DPORT_APP_CACHE_CTRL1

app_cache_lock_0_addr: Reg<APP_CACHE_LOCK_0_ADDR_SPEC>

0x60 - DPORT_APP_CACHE_LOCK_0_ADDR

app_cache_lock_1_addr: Reg<APP_CACHE_LOCK_1_ADDR_SPEC>

0x64 - DPORT_APP_CACHE_LOCK_1_ADDR

app_cache_lock_2_addr: Reg<APP_CACHE_LOCK_2_ADDR_SPEC>

0x68 - DPORT_APP_CACHE_LOCK_2_ADDR

app_cache_lock_3_addr: Reg<APP_CACHE_LOCK_3_ADDR_SPEC>

0x6c - DPORT_APP_CACHE_LOCK_3_ADDR

tracemem_mux_mode: Reg<TRACEMEM_MUX_MODE_SPEC>

0x70 - DPORT_TRACEMEM_MUX_MODE

pro_tracemem_ena: Reg<PRO_TRACEMEM_ENA_SPEC>

0x74 - DPORT_PRO_TRACEMEM_ENA

app_tracemem_ena: Reg<APP_TRACEMEM_ENA_SPEC>

0x78 - DPORT_APP_TRACEMEM_ENA

cache_mux_mode: Reg<CACHE_MUX_MODE_SPEC>

0x7c - DPORT_CACHE_MUX_MODE

immu_page_mode: Reg<IMMU_PAGE_MODE_SPEC>

0x80 - DPORT_IMMU_PAGE_MODE

dmmu_page_mode: Reg<DMMU_PAGE_MODE_SPEC>

0x84 - DPORT_DMMU_PAGE_MODE

rom_mpu_ena: Reg<ROM_MPU_ENA_SPEC>

0x88 - DPORT_ROM_MPU_ENA

mem_pd_mask: Reg<MEM_PD_MASK_SPEC>

0x8c - DPORT_MEM_PD_MASK

rom_pd_ctrl: Reg<ROM_PD_CTRL_SPEC>

0x90 - DPORT_ROM_PD_CTRL

rom_fo_ctrl: Reg<ROM_FO_CTRL_SPEC>

0x94 - DPORT_ROM_FO_CTRL

sram_pd_ctrl_0: Reg<SRAM_PD_CTRL_0_SPEC>

0x98 - DPORT_SRAM_PD_CTRL_0

sram_pd_ctrl_1: Reg<SRAM_PD_CTRL_1_SPEC>

0x9c - DPORT_SRAM_PD_CTRL_1

sram_fo_ctrl_0: Reg<SRAM_FO_CTRL_0_SPEC>

0xa0 - DPORT_SRAM_FO_CTRL_0

sram_fo_ctrl_1: Reg<SRAM_FO_CTRL_1_SPEC>

0xa4 - DPORT_SRAM_FO_CTRL_1

iram_dram_ahb_sel: Reg<IRAM_DRAM_AHB_SEL_SPEC>

0xa8 - DPORT_IRAM_DRAM_AHB_SEL

tag_fo_ctrl: Reg<TAG_FO_CTRL_SPEC>

0xac - DPORT_TAG_FO_CTRL

ahb_lite_mask: Reg<AHB_LITE_MASK_SPEC>

0xb0 - DPORT_AHB_LITE_MASK

ahb_mpu_table_0: Reg<AHB_MPU_TABLE_0_SPEC>

0xb4 - DPORT_AHB_MPU_TABLE_0

ahb_mpu_table_1: Reg<AHB_MPU_TABLE_1_SPEC>

0xb8 - DPORT_AHB_MPU_TABLE_1

host_inf_sel: Reg<HOST_INF_SEL_SPEC>

0xbc - DPORT_HOST_INF_SEL

perip_clk_en: Reg<PERIP_CLK_EN_SPEC>

0xc0 - DPORT_PERIP_CLK_EN

perip_rst_en: Reg<PERIP_RST_EN_SPEC>

0xc4 - DPORT_PERIP_RST_EN

wifi_clk_en: Reg<WIFI_CLK_EN_SPEC>

0xcc - DPORT_WIFI_CLK_EN

core_rst_en: Reg<CORE_RST_EN_SPEC>

0xd0 - DPORT_CORE_RST_EN

bt_lpck_div_int: Reg<BT_LPCK_DIV_INT_SPEC>

0xd4 - DPORT_BT_LPCK_DIV_INT

bt_lpck_div_frac: Reg<BT_LPCK_DIV_FRAC_SPEC>

0xd8 - DPORT_BT_LPCK_DIV_FRAC

cpu_intr_from_cpu_0: Reg<CPU_INTR_FROM_CPU_0_SPEC>

0xdc - DPORT_CPU_INTR_FROM_CPU_0

cpu_intr_from_cpu_1: Reg<CPU_INTR_FROM_CPU_1_SPEC>

0xe0 - DPORT_CPU_INTR_FROM_CPU_1

cpu_intr_from_cpu_2: Reg<CPU_INTR_FROM_CPU_2_SPEC>

0xe4 - DPORT_CPU_INTR_FROM_CPU_2

cpu_intr_from_cpu_3: Reg<CPU_INTR_FROM_CPU_3_SPEC>

0xe8 - DPORT_CPU_INTR_FROM_CPU_3

pro_intr_status_0: Reg<PRO_INTR_STATUS_0_SPEC>

0xec - DPORT_PRO_INTR_STATUS_0

pro_intr_status_1: Reg<PRO_INTR_STATUS_1_SPEC>

0xf0 - DPORT_PRO_INTR_STATUS_1

pro_intr_status_2: Reg<PRO_INTR_STATUS_2_SPEC>

0xf4 - DPORT_PRO_INTR_STATUS_2

app_intr_status_0: Reg<APP_INTR_STATUS_0_SPEC>

0xf8 - DPORT_APP_INTR_STATUS_0

app_intr_status_1: Reg<APP_INTR_STATUS_1_SPEC>

0xfc - DPORT_APP_INTR_STATUS_1

app_intr_status_2: Reg<APP_INTR_STATUS_2_SPEC>

0x100 - DPORT_APP_INTR_STATUS_2

pro_mac_intr_map: Reg<PRO_MAC_INTR_MAP_SPEC>

0x104 - DPORT_PRO_MAC_INTR_MAP

pro_mac_nmi_map: Reg<PRO_MAC_NMI_MAP_SPEC>

0x108 - DPORT_PRO_MAC_NMI_MAP

pro_bb_int_map: Reg<PRO_BB_INT_MAP_SPEC>

0x10c - DPORT_PRO_BB_INT_MAP

pro_bt_mac_int_map: Reg<PRO_BT_MAC_INT_MAP_SPEC>

0x110 - DPORT_PRO_BT_MAC_INT_MAP

pro_bt_bb_int_map: Reg<PRO_BT_BB_INT_MAP_SPEC>

0x114 - DPORT_PRO_BT_BB_INT_MAP

pro_bt_bb_nmi_map: Reg<PRO_BT_BB_NMI_MAP_SPEC>

0x118 - DPORT_PRO_BT_BB_NMI_MAP

pro_rwbt_irq_map: Reg<PRO_RWBT_IRQ_MAP_SPEC>

0x11c - DPORT_PRO_RWBT_IRQ_MAP

pro_rwble_irq_map: Reg<PRO_RWBLE_IRQ_MAP_SPEC>

0x120 - DPORT_PRO_RWBLE_IRQ_MAP

pro_rwbt_nmi_map: Reg<PRO_RWBT_NMI_MAP_SPEC>

0x124 - DPORT_PRO_RWBT_NMI_MAP

pro_rwble_nmi_map: Reg<PRO_RWBLE_NMI_MAP_SPEC>

0x128 - DPORT_PRO_RWBLE_NMI_MAP

pro_slc0_intr_map: Reg<PRO_SLC0_INTR_MAP_SPEC>

0x12c - DPORT_PRO_SLC0_INTR_MAP

pro_slc1_intr_map: Reg<PRO_SLC1_INTR_MAP_SPEC>

0x130 - DPORT_PRO_SLC1_INTR_MAP

pro_uhci0_intr_map: Reg<PRO_UHCI0_INTR_MAP_SPEC>

0x134 - DPORT_PRO_UHCI0_INTR_MAP

pro_uhci1_intr_map: Reg<PRO_UHCI1_INTR_MAP_SPEC>

0x138 - DPORT_PRO_UHCI1_INTR_MAP

pro_tg_t0_level_int_map: Reg<PRO_TG_T0_LEVEL_INT_MAP_SPEC>

0x13c - DPORT_PRO_TG_T0_LEVEL_INT_MAP

pro_tg_t1_level_int_map: Reg<PRO_TG_T1_LEVEL_INT_MAP_SPEC>

0x140 - DPORT_PRO_TG_T1_LEVEL_INT_MAP

pro_tg_wdt_level_int_map: Reg<PRO_TG_WDT_LEVEL_INT_MAP_SPEC>

0x144 - DPORT_PRO_TG_WDT_LEVEL_INT_MAP

pro_tg_lact_level_int_map: Reg<PRO_TG_LACT_LEVEL_INT_MAP_SPEC>

0x148 - DPORT_PRO_TG_LACT_LEVEL_INT_MAP

pro_tg1_t0_level_int_map: Reg<PRO_TG1_T0_LEVEL_INT_MAP_SPEC>

0x14c - DPORT_PRO_TG1_T0_LEVEL_INT_MAP

pro_tg1_t1_level_int_map: Reg<PRO_TG1_T1_LEVEL_INT_MAP_SPEC>

0x150 - DPORT_PRO_TG1_T1_LEVEL_INT_MAP

pro_tg1_wdt_level_int_map: Reg<PRO_TG1_WDT_LEVEL_INT_MAP_SPEC>

0x154 - DPORT_PRO_TG1_WDT_LEVEL_INT_MAP

pro_tg1_lact_level_int_map: Reg<PRO_TG1_LACT_LEVEL_INT_MAP_SPEC>

0x158 - DPORT_PRO_TG1_LACT_LEVEL_INT_MAP

pro_gpio_interrupt_map: Reg<PRO_GPIO_INTERRUPT_MAP_SPEC>

0x15c - DPORT_PRO_GPIO_INTERRUPT_MAP

pro_gpio_interrupt_nmi_map: Reg<PRO_GPIO_INTERRUPT_NMI_MAP_SPEC>

0x160 - DPORT_PRO_GPIO_INTERRUPT_NMI_MAP

pro_cpu_intr_from_cpu_0_map: Reg<PRO_CPU_INTR_FROM_CPU_0_MAP_SPEC>

0x164 - DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP

pro_cpu_intr_from_cpu_1_map: Reg<PRO_CPU_INTR_FROM_CPU_1_MAP_SPEC>

0x168 - DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP

pro_cpu_intr_from_cpu_2_map: Reg<PRO_CPU_INTR_FROM_CPU_2_MAP_SPEC>

0x16c - DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP

pro_cpu_intr_from_cpu_3_map: Reg<PRO_CPU_INTR_FROM_CPU_3_MAP_SPEC>

0x170 - DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP

pro_spi_intr_0_map: Reg<PRO_SPI_INTR_0_MAP_SPEC>

0x174 - DPORT_PRO_SPI_INTR_0_MAP

pro_spi_intr_1_map: Reg<PRO_SPI_INTR_1_MAP_SPEC>

0x178 - DPORT_PRO_SPI_INTR_1_MAP

pro_spi_intr_2_map: Reg<PRO_SPI_INTR_2_MAP_SPEC>

0x17c - DPORT_PRO_SPI_INTR_2_MAP

pro_spi_intr_3_map: Reg<PRO_SPI_INTR_3_MAP_SPEC>

0x180 - DPORT_PRO_SPI_INTR_3_MAP

pro_i2s0_int_map: Reg<PRO_I2S0_INT_MAP_SPEC>

0x184 - DPORT_PRO_I2S0_INT_MAP

pro_i2s1_int_map: Reg<PRO_I2S1_INT_MAP_SPEC>

0x188 - DPORT_PRO_I2S1_INT_MAP

pro_uart_intr_map: Reg<PRO_UART_INTR_MAP_SPEC>

0x18c - DPORT_PRO_UART_INTR_MAP

pro_uart1_intr_map: Reg<PRO_UART1_INTR_MAP_SPEC>

0x190 - DPORT_PRO_UART1_INTR_MAP

pro_uart2_intr_map: Reg<PRO_UART2_INTR_MAP_SPEC>

0x194 - DPORT_PRO_UART2_INTR_MAP

pro_sdio_host_interrupt_map: Reg<PRO_SDIO_HOST_INTERRUPT_MAP_SPEC>

0x198 - DPORT_PRO_SDIO_HOST_INTERRUPT_MAP

pro_emac_int_map: Reg<PRO_EMAC_INT_MAP_SPEC>

0x19c - DPORT_PRO_EMAC_INT_MAP

pro_pwm0_intr_map: Reg<PRO_PWM0_INTR_MAP_SPEC>

0x1a0 - DPORT_PRO_PWM0_INTR_MAP

pro_pwm1_intr_map: Reg<PRO_PWM1_INTR_MAP_SPEC>

0x1a4 - DPORT_PRO_PWM1_INTR_MAP

pro_pwm2_intr_map: Reg<PRO_PWM2_INTR_MAP_SPEC>

0x1a8 - DPORT_PRO_PWM2_INTR_MAP

pro_pwm3_intr_map: Reg<PRO_PWM3_INTR_MAP_SPEC>

0x1ac - DPORT_PRO_PWM3_INTR_MAP

pro_ledc_int_map: Reg<PRO_LEDC_INT_MAP_SPEC>

0x1b0 - DPORT_PRO_LEDC_INT_MAP

pro_efuse_int_map: Reg<PRO_EFUSE_INT_MAP_SPEC>

0x1b4 - DPORT_PRO_EFUSE_INT_MAP

pro_can_int_map: Reg<PRO_CAN_INT_MAP_SPEC>

0x1b8 - DPORT_PRO_CAN_INT_MAP

pro_rtc_core_intr_map: Reg<PRO_RTC_CORE_INTR_MAP_SPEC>

0x1bc - DPORT_PRO_RTC_CORE_INTR_MAP

pro_rmt_intr_map: Reg<PRO_RMT_INTR_MAP_SPEC>

0x1c0 - DPORT_PRO_RMT_INTR_MAP

pro_pcnt_intr_map: Reg<PRO_PCNT_INTR_MAP_SPEC>

0x1c4 - DPORT_PRO_PCNT_INTR_MAP

pro_i2c_ext0_intr_map: Reg<PRO_I2C_EXT0_INTR_MAP_SPEC>

0x1c8 - DPORT_PRO_I2C_EXT0_INTR_MAP

pro_i2c_ext1_intr_map: Reg<PRO_I2C_EXT1_INTR_MAP_SPEC>

0x1cc - DPORT_PRO_I2C_EXT1_INTR_MAP

pro_rsa_intr_map: Reg<PRO_RSA_INTR_MAP_SPEC>

0x1d0 - DPORT_PRO_RSA_INTR_MAP

pro_spi1_dma_int_map: Reg<PRO_SPI1_DMA_INT_MAP_SPEC>

0x1d4 - DPORT_PRO_SPI1_DMA_INT_MAP

pro_spi2_dma_int_map: Reg<PRO_SPI2_DMA_INT_MAP_SPEC>

0x1d8 - DPORT_PRO_SPI2_DMA_INT_MAP

pro_spi3_dma_int_map: Reg<PRO_SPI3_DMA_INT_MAP_SPEC>

0x1dc - DPORT_PRO_SPI3_DMA_INT_MAP

pro_wdg_int_map: Reg<PRO_WDG_INT_MAP_SPEC>

0x1e0 - DPORT_PRO_WDG_INT_MAP

pro_timer_int1_map: Reg<PRO_TIMER_INT1_MAP_SPEC>

0x1e4 - DPORT_PRO_TIMER_INT1_MAP

pro_timer_int2_map: Reg<PRO_TIMER_INT2_MAP_SPEC>

0x1e8 - DPORT_PRO_TIMER_INT2_MAP

pro_tg_t0_edge_int_map: Reg<PRO_TG_T0_EDGE_INT_MAP_SPEC>

0x1ec - DPORT_PRO_TG_T0_EDGE_INT_MAP

pro_tg_t1_edge_int_map: Reg<PRO_TG_T1_EDGE_INT_MAP_SPEC>

0x1f0 - DPORT_PRO_TG_T1_EDGE_INT_MAP

pro_tg_wdt_edge_int_map: Reg<PRO_TG_WDT_EDGE_INT_MAP_SPEC>

0x1f4 - DPORT_PRO_TG_WDT_EDGE_INT_MAP

pro_tg_lact_edge_int_map: Reg<PRO_TG_LACT_EDGE_INT_MAP_SPEC>

0x1f8 - DPORT_PRO_TG_LACT_EDGE_INT_MAP

pro_tg1_t0_edge_int_map: Reg<PRO_TG1_T0_EDGE_INT_MAP_SPEC>

0x1fc - DPORT_PRO_TG1_T0_EDGE_INT_MAP

pro_tg1_t1_edge_int_map: Reg<PRO_TG1_T1_EDGE_INT_MAP_SPEC>

0x200 - DPORT_PRO_TG1_T1_EDGE_INT_MAP

pro_tg1_wdt_edge_int_map: Reg<PRO_TG1_WDT_EDGE_INT_MAP_SPEC>

0x204 - DPORT_PRO_TG1_WDT_EDGE_INT_MAP

pro_tg1_lact_edge_int_map: Reg<PRO_TG1_LACT_EDGE_INT_MAP_SPEC>

0x208 - DPORT_PRO_TG1_LACT_EDGE_INT_MAP

pro_mmu_ia_int_map: Reg<PRO_MMU_IA_INT_MAP_SPEC>

0x20c - DPORT_PRO_MMU_IA_INT_MAP

pro_mpu_ia_int_map: Reg<PRO_MPU_IA_INT_MAP_SPEC>

0x210 - DPORT_PRO_MPU_IA_INT_MAP

pro_cache_ia_int_map: Reg<PRO_CACHE_IA_INT_MAP_SPEC>

0x214 - DPORT_PRO_CACHE_IA_INT_MAP

app_mac_intr_map: Reg<APP_MAC_INTR_MAP_SPEC>

0x218 - DPORT_APP_MAC_INTR_MAP

app_mac_nmi_map: Reg<APP_MAC_NMI_MAP_SPEC>

0x21c - DPORT_APP_MAC_NMI_MAP

app_bb_int_map: Reg<APP_BB_INT_MAP_SPEC>

0x220 - DPORT_APP_BB_INT_MAP

app_bt_mac_int_map: Reg<APP_BT_MAC_INT_MAP_SPEC>

0x224 - DPORT_APP_BT_MAC_INT_MAP

app_bt_bb_int_map: Reg<APP_BT_BB_INT_MAP_SPEC>

0x228 - DPORT_APP_BT_BB_INT_MAP

app_bt_bb_nmi_map: Reg<APP_BT_BB_NMI_MAP_SPEC>

0x22c - DPORT_APP_BT_BB_NMI_MAP

app_rwbt_irq_map: Reg<APP_RWBT_IRQ_MAP_SPEC>

0x230 - DPORT_APP_RWBT_IRQ_MAP

app_rwble_irq_map: Reg<APP_RWBLE_IRQ_MAP_SPEC>

0x234 - DPORT_APP_RWBLE_IRQ_MAP

app_rwbt_nmi_map: Reg<APP_RWBT_NMI_MAP_SPEC>

0x238 - DPORT_APP_RWBT_NMI_MAP

app_rwble_nmi_map: Reg<APP_RWBLE_NMI_MAP_SPEC>

0x23c - DPORT_APP_RWBLE_NMI_MAP

app_slc0_intr_map: Reg<APP_SLC0_INTR_MAP_SPEC>

0x240 - DPORT_APP_SLC0_INTR_MAP

app_slc1_intr_map: Reg<APP_SLC1_INTR_MAP_SPEC>

0x244 - DPORT_APP_SLC1_INTR_MAP

app_uhci0_intr_map: Reg<APP_UHCI0_INTR_MAP_SPEC>

0x248 - DPORT_APP_UHCI0_INTR_MAP

app_uhci1_intr_map: Reg<APP_UHCI1_INTR_MAP_SPEC>

0x24c - DPORT_APP_UHCI1_INTR_MAP

app_tg_t0_level_int_map: Reg<APP_TG_T0_LEVEL_INT_MAP_SPEC>

0x250 - DPORT_APP_TG_T0_LEVEL_INT_MAP

app_tg_t1_level_int_map: Reg<APP_TG_T1_LEVEL_INT_MAP_SPEC>

0x254 - DPORT_APP_TG_T1_LEVEL_INT_MAP

app_tg_wdt_level_int_map: Reg<APP_TG_WDT_LEVEL_INT_MAP_SPEC>

0x258 - DPORT_APP_TG_WDT_LEVEL_INT_MAP

app_tg_lact_level_int_map: Reg<APP_TG_LACT_LEVEL_INT_MAP_SPEC>

0x25c - DPORT_APP_TG_LACT_LEVEL_INT_MAP

app_tg1_t0_level_int_map: Reg<APP_TG1_T0_LEVEL_INT_MAP_SPEC>

0x260 - DPORT_APP_TG1_T0_LEVEL_INT_MAP

app_tg1_t1_level_int_map: Reg<APP_TG1_T1_LEVEL_INT_MAP_SPEC>

0x264 - DPORT_APP_TG1_T1_LEVEL_INT_MAP

app_tg1_wdt_level_int_map: Reg<APP_TG1_WDT_LEVEL_INT_MAP_SPEC>

0x268 - DPORT_APP_TG1_WDT_LEVEL_INT_MAP

app_tg1_lact_level_int_map: Reg<APP_TG1_LACT_LEVEL_INT_MAP_SPEC>

0x26c - DPORT_APP_TG1_LACT_LEVEL_INT_MAP

app_gpio_interrupt_map: Reg<APP_GPIO_INTERRUPT_MAP_SPEC>

0x270 - DPORT_APP_GPIO_INTERRUPT_MAP

app_gpio_interrupt_nmi_map: Reg<APP_GPIO_INTERRUPT_NMI_MAP_SPEC>

0x274 - DPORT_APP_GPIO_INTERRUPT_NMI_MAP

app_cpu_intr_from_cpu_0_map: Reg<APP_CPU_INTR_FROM_CPU_0_MAP_SPEC>

0x278 - DPORT_APP_CPU_INTR_FROM_CPU_0_MAP

app_cpu_intr_from_cpu_1_map: Reg<APP_CPU_INTR_FROM_CPU_1_MAP_SPEC>

0x27c - DPORT_APP_CPU_INTR_FROM_CPU_1_MAP

app_cpu_intr_from_cpu_2_map: Reg<APP_CPU_INTR_FROM_CPU_2_MAP_SPEC>

0x280 - DPORT_APP_CPU_INTR_FROM_CPU_2_MAP

app_cpu_intr_from_cpu_3_map: Reg<APP_CPU_INTR_FROM_CPU_3_MAP_SPEC>

0x284 - DPORT_APP_CPU_INTR_FROM_CPU_3_MAP

app_spi_intr_0_map: Reg<APP_SPI_INTR_0_MAP_SPEC>

0x288 - DPORT_APP_SPI_INTR_0_MAP

app_spi_intr_1_map: Reg<APP_SPI_INTR_1_MAP_SPEC>

0x28c - DPORT_APP_SPI_INTR_1_MAP

app_spi_intr_2_map: Reg<APP_SPI_INTR_2_MAP_SPEC>

0x290 - DPORT_APP_SPI_INTR_2_MAP

app_spi_intr_3_map: Reg<APP_SPI_INTR_3_MAP_SPEC>

0x294 - DPORT_APP_SPI_INTR_3_MAP

app_i2s0_int_map: Reg<APP_I2S0_INT_MAP_SPEC>

0x298 - DPORT_APP_I2S0_INT_MAP

app_i2s1_int_map: Reg<APP_I2S1_INT_MAP_SPEC>

0x29c - DPORT_APP_I2S1_INT_MAP

app_uart_intr_map: Reg<APP_UART_INTR_MAP_SPEC>

0x2a0 - DPORT_APP_UART_INTR_MAP

app_uart1_intr_map: Reg<APP_UART1_INTR_MAP_SPEC>

0x2a4 - DPORT_APP_UART1_INTR_MAP

app_uart2_intr_map: Reg<APP_UART2_INTR_MAP_SPEC>

0x2a8 - DPORT_APP_UART2_INTR_MAP

app_sdio_host_interrupt_map: Reg<APP_SDIO_HOST_INTERRUPT_MAP_SPEC>

0x2ac - DPORT_APP_SDIO_HOST_INTERRUPT_MAP

app_emac_int_map: Reg<APP_EMAC_INT_MAP_SPEC>

0x2b0 - DPORT_APP_EMAC_INT_MAP

app_pwm0_intr_map: Reg<APP_PWM0_INTR_MAP_SPEC>

0x2b4 - DPORT_APP_PWM0_INTR_MAP

app_pwm1_intr_map: Reg<APP_PWM1_INTR_MAP_SPEC>

0x2b8 - DPORT_APP_PWM1_INTR_MAP

app_pwm2_intr_map: Reg<APP_PWM2_INTR_MAP_SPEC>

0x2bc - DPORT_APP_PWM2_INTR_MAP

app_pwm3_intr_map: Reg<APP_PWM3_INTR_MAP_SPEC>

0x2c0 - DPORT_APP_PWM3_INTR_MAP

app_ledc_int_map: Reg<APP_LEDC_INT_MAP_SPEC>

0x2c4 - DPORT_APP_LEDC_INT_MAP

app_efuse_int_map: Reg<APP_EFUSE_INT_MAP_SPEC>

0x2c8 - DPORT_APP_EFUSE_INT_MAP

app_can_int_map: Reg<APP_CAN_INT_MAP_SPEC>

0x2cc - DPORT_APP_CAN_INT_MAP

app_rtc_core_intr_map: Reg<APP_RTC_CORE_INTR_MAP_SPEC>

0x2d0 - DPORT_APP_RTC_CORE_INTR_MAP

app_rmt_intr_map: Reg<APP_RMT_INTR_MAP_SPEC>

0x2d4 - DPORT_APP_RMT_INTR_MAP

app_pcnt_intr_map: Reg<APP_PCNT_INTR_MAP_SPEC>

0x2d8 - DPORT_APP_PCNT_INTR_MAP

app_i2c_ext0_intr_map: Reg<APP_I2C_EXT0_INTR_MAP_SPEC>

0x2dc - DPORT_APP_I2C_EXT0_INTR_MAP

app_i2c_ext1_intr_map: Reg<APP_I2C_EXT1_INTR_MAP_SPEC>

0x2e0 - DPORT_APP_I2C_EXT1_INTR_MAP

app_rsa_intr_map: Reg<APP_RSA_INTR_MAP_SPEC>

0x2e4 - DPORT_APP_RSA_INTR_MAP

app_spi1_dma_int_map: Reg<APP_SPI1_DMA_INT_MAP_SPEC>

0x2e8 - DPORT_APP_SPI1_DMA_INT_MAP

app_spi2_dma_int_map: Reg<APP_SPI2_DMA_INT_MAP_SPEC>

0x2ec - DPORT_APP_SPI2_DMA_INT_MAP

app_spi3_dma_int_map: Reg<APP_SPI3_DMA_INT_MAP_SPEC>

0x2f0 - DPORT_APP_SPI3_DMA_INT_MAP

app_wdg_int_map: Reg<APP_WDG_INT_MAP_SPEC>

0x2f4 - DPORT_APP_WDG_INT_MAP

app_timer_int1_map: Reg<APP_TIMER_INT1_MAP_SPEC>

0x2f8 - DPORT_APP_TIMER_INT1_MAP

app_timer_int2_map: Reg<APP_TIMER_INT2_MAP_SPEC>

0x2fc - DPORT_APP_TIMER_INT2_MAP

app_tg_t0_edge_int_map: Reg<APP_TG_T0_EDGE_INT_MAP_SPEC>

0x300 - DPORT_APP_TG_T0_EDGE_INT_MAP

app_tg_t1_edge_int_map: Reg<APP_TG_T1_EDGE_INT_MAP_SPEC>

0x304 - DPORT_APP_TG_T1_EDGE_INT_MAP

app_tg_wdt_edge_int_map: Reg<APP_TG_WDT_EDGE_INT_MAP_SPEC>

0x308 - DPORT_APP_TG_WDT_EDGE_INT_MAP

app_tg_lact_edge_int_map: Reg<APP_TG_LACT_EDGE_INT_MAP_SPEC>

0x30c - DPORT_APP_TG_LACT_EDGE_INT_MAP

app_tg1_t0_edge_int_map: Reg<APP_TG1_T0_EDGE_INT_MAP_SPEC>

0x310 - DPORT_APP_TG1_T0_EDGE_INT_MAP

app_tg1_t1_edge_int_map: Reg<APP_TG1_T1_EDGE_INT_MAP_SPEC>

0x314 - DPORT_APP_TG1_T1_EDGE_INT_MAP

app_tg1_wdt_edge_int_map: Reg<APP_TG1_WDT_EDGE_INT_MAP_SPEC>

0x318 - DPORT_APP_TG1_WDT_EDGE_INT_MAP

app_tg1_lact_edge_int_map: Reg<APP_TG1_LACT_EDGE_INT_MAP_SPEC>

0x31c - DPORT_APP_TG1_LACT_EDGE_INT_MAP

app_mmu_ia_int_map: Reg<APP_MMU_IA_INT_MAP_SPEC>

0x320 - DPORT_APP_MMU_IA_INT_MAP

app_mpu_ia_int_map: Reg<APP_MPU_IA_INT_MAP_SPEC>

0x324 - DPORT_APP_MPU_IA_INT_MAP

app_cache_ia_int_map: Reg<APP_CACHE_IA_INT_MAP_SPEC>

0x328 - DPORT_APP_CACHE_IA_INT_MAP

ahblite_mpu_table_uart: Reg<AHBLITE_MPU_TABLE_UART_SPEC>

0x32c - DPORT_AHBLITE_MPU_TABLE_UART

ahblite_mpu_table_spi1: Reg<AHBLITE_MPU_TABLE_SPI1_SPEC>

0x330 - DPORT_AHBLITE_MPU_TABLE_SPI1

ahblite_mpu_table_spi0: Reg<AHBLITE_MPU_TABLE_SPI0_SPEC>

0x334 - DPORT_AHBLITE_MPU_TABLE_SPI0

ahblite_mpu_table_gpio: Reg<AHBLITE_MPU_TABLE_GPIO_SPEC>

0x338 - DPORT_AHBLITE_MPU_TABLE_GPIO

ahblite_mpu_table_fe2: Reg<AHBLITE_MPU_TABLE_FE2_SPEC>

0x33c - DPORT_AHBLITE_MPU_TABLE_FE2

ahblite_mpu_table_fe: Reg<AHBLITE_MPU_TABLE_FE_SPEC>

0x340 - DPORT_AHBLITE_MPU_TABLE_FE

ahblite_mpu_table_timer: Reg<AHBLITE_MPU_TABLE_TIMER_SPEC>

0x344 - DPORT_AHBLITE_MPU_TABLE_TIMER

ahblite_mpu_table_rtc: Reg<AHBLITE_MPU_TABLE_RTC_SPEC>

0x348 - DPORT_AHBLITE_MPU_TABLE_RTC

ahblite_mpu_table_io_mux: Reg<AHBLITE_MPU_TABLE_IO_MUX_SPEC>

0x34c - DPORT_AHBLITE_MPU_TABLE_IO_MUX

ahblite_mpu_table_wdg: Reg<AHBLITE_MPU_TABLE_WDG_SPEC>

0x350 - DPORT_AHBLITE_MPU_TABLE_WDG

ahblite_mpu_table_hinf: Reg<AHBLITE_MPU_TABLE_HINF_SPEC>

0x354 - DPORT_AHBLITE_MPU_TABLE_HINF

ahblite_mpu_table_uhci1: Reg<AHBLITE_MPU_TABLE_UHCI1_SPEC>

0x358 - DPORT_AHBLITE_MPU_TABLE_UHCI1

ahblite_mpu_table_misc: Reg<AHBLITE_MPU_TABLE_MISC_SPEC>

0x35c - DPORT_AHBLITE_MPU_TABLE_MISC

ahblite_mpu_table_i2c: Reg<AHBLITE_MPU_TABLE_I2C_SPEC>

0x360 - DPORT_AHBLITE_MPU_TABLE_I2C

ahblite_mpu_table_i2s0: Reg<AHBLITE_MPU_TABLE_I2S0_SPEC>

0x364 - DPORT_AHBLITE_MPU_TABLE_I2S0

ahblite_mpu_table_uart1: Reg<AHBLITE_MPU_TABLE_UART1_SPEC>

0x368 - DPORT_AHBLITE_MPU_TABLE_UART1

ahblite_mpu_table_bt: Reg<AHBLITE_MPU_TABLE_BT_SPEC>

0x36c - DPORT_AHBLITE_MPU_TABLE_BT

ahblite_mpu_table_bt_buffer: Reg<AHBLITE_MPU_TABLE_BT_BUFFER_SPEC>

0x370 - DPORT_AHBLITE_MPU_TABLE_BT_BUFFER

ahblite_mpu_table_i2c_ext0: Reg<AHBLITE_MPU_TABLE_I2C_EXT0_SPEC>

0x374 - DPORT_AHBLITE_MPU_TABLE_I2C_EXT0

ahblite_mpu_table_uhci0: Reg<AHBLITE_MPU_TABLE_UHCI0_SPEC>

0x378 - DPORT_AHBLITE_MPU_TABLE_UHCI0

ahblite_mpu_table_slchost: Reg<AHBLITE_MPU_TABLE_SLCHOST_SPEC>

0x37c - DPORT_AHBLITE_MPU_TABLE_SLCHOST

ahblite_mpu_table_rmt: Reg<AHBLITE_MPU_TABLE_RMT_SPEC>

0x380 - DPORT_AHBLITE_MPU_TABLE_RMT

ahblite_mpu_table_pcnt: Reg<AHBLITE_MPU_TABLE_PCNT_SPEC>

0x384 - DPORT_AHBLITE_MPU_TABLE_PCNT

ahblite_mpu_table_slc: Reg<AHBLITE_MPU_TABLE_SLC_SPEC>

0x388 - DPORT_AHBLITE_MPU_TABLE_SLC

ahblite_mpu_table_ledc: Reg<AHBLITE_MPU_TABLE_LEDC_SPEC>

0x38c - DPORT_AHBLITE_MPU_TABLE_LEDC

ahblite_mpu_table_efuse: Reg<AHBLITE_MPU_TABLE_EFUSE_SPEC>

0x390 - DPORT_AHBLITE_MPU_TABLE_EFUSE

ahblite_mpu_table_spi_encrypt: Reg<AHBLITE_MPU_TABLE_SPI_ENCRYPT_SPEC>

0x394 - DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT

ahblite_mpu_table_bb: Reg<AHBLITE_MPU_TABLE_BB_SPEC>

0x398 - DPORT_AHBLITE_MPU_TABLE_BB

ahblite_mpu_table_pwm0: Reg<AHBLITE_MPU_TABLE_PWM0_SPEC>

0x39c - DPORT_AHBLITE_MPU_TABLE_PWM0

ahblite_mpu_table_timergroup: Reg<AHBLITE_MPU_TABLE_TIMERGROUP_SPEC>

0x3a0 - DPORT_AHBLITE_MPU_TABLE_TIMERGROUP

ahblite_mpu_table_timergroup1: Reg<AHBLITE_MPU_TABLE_TIMERGROUP1_SPEC>

0x3a4 - DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1

ahblite_mpu_table_spi2: Reg<AHBLITE_MPU_TABLE_SPI2_SPEC>

0x3a8 - DPORT_AHBLITE_MPU_TABLE_SPI2

ahblite_mpu_table_spi3: Reg<AHBLITE_MPU_TABLE_SPI3_SPEC>

0x3ac - DPORT_AHBLITE_MPU_TABLE_SPI3

ahblite_mpu_table_apb_ctrl: Reg<AHBLITE_MPU_TABLE_APB_CTRL_SPEC>

0x3b0 - DPORT_AHBLITE_MPU_TABLE_APB_CTRL

ahblite_mpu_table_i2c_ext1: Reg<AHBLITE_MPU_TABLE_I2C_EXT1_SPEC>

0x3b4 - DPORT_AHBLITE_MPU_TABLE_I2C_EXT1

ahblite_mpu_table_sdio_host: Reg<AHBLITE_MPU_TABLE_SDIO_HOST_SPEC>

0x3b8 - DPORT_AHBLITE_MPU_TABLE_SDIO_HOST

ahblite_mpu_table_emac: Reg<AHBLITE_MPU_TABLE_EMAC_SPEC>

0x3bc - DPORT_AHBLITE_MPU_TABLE_EMAC

ahblite_mpu_table_can: Reg<AHBLITE_MPU_TABLE_CAN_SPEC>

0x3c0 - DPORT_AHBLITE_MPU_TABLE_CAN

ahblite_mpu_table_pwm1: Reg<AHBLITE_MPU_TABLE_PWM1_SPEC>

0x3c4 - DPORT_AHBLITE_MPU_TABLE_PWM1

ahblite_mpu_table_i2s1: Reg<AHBLITE_MPU_TABLE_I2S1_SPEC>

0x3c8 - DPORT_AHBLITE_MPU_TABLE_I2S1

ahblite_mpu_table_uart2: Reg<AHBLITE_MPU_TABLE_UART2_SPEC>

0x3cc - DPORT_AHBLITE_MPU_TABLE_UART2

ahblite_mpu_table_pwm2: Reg<AHBLITE_MPU_TABLE_PWM2_SPEC>

0x3d0 - DPORT_AHBLITE_MPU_TABLE_PWM2

ahblite_mpu_table_pwm3: Reg<AHBLITE_MPU_TABLE_PWM3_SPEC>

0x3d4 - DPORT_AHBLITE_MPU_TABLE_PWM3

ahblite_mpu_table_rwbt: Reg<AHBLITE_MPU_TABLE_RWBT_SPEC>

0x3d8 - DPORT_AHBLITE_MPU_TABLE_RWBT

ahblite_mpu_table_btmac: Reg<AHBLITE_MPU_TABLE_BTMAC_SPEC>

0x3dc - DPORT_AHBLITE_MPU_TABLE_BTMAC

ahblite_mpu_table_wifimac: Reg<AHBLITE_MPU_TABLE_WIFIMAC_SPEC>

0x3e0 - DPORT_AHBLITE_MPU_TABLE_WIFIMAC

ahblite_mpu_table_pwr: Reg<AHBLITE_MPU_TABLE_PWR_SPEC>

0x3e4 - DPORT_AHBLITE_MPU_TABLE_PWR

mem_access_dbug0: Reg<MEM_ACCESS_DBUG0_SPEC>

0x3e8 - DPORT_MEM_ACCESS_DBUG0

mem_access_dbug1: Reg<MEM_ACCESS_DBUG1_SPEC>

0x3ec - DPORT_MEM_ACCESS_DBUG1

pro_dcache_dbug0: Reg<PRO_DCACHE_DBUG0_SPEC>

0x3f0 - DPORT_PRO_DCACHE_DBUG0

pro_dcache_dbug1: Reg<PRO_DCACHE_DBUG1_SPEC>

0x3f4 - DPORT_PRO_DCACHE_DBUG1

pro_dcache_dbug2: Reg<PRO_DCACHE_DBUG2_SPEC>

0x3f8 - DPORT_PRO_DCACHE_DBUG2

pro_dcache_dbug3: Reg<PRO_DCACHE_DBUG3_SPEC>

0x3fc - DPORT_PRO_DCACHE_DBUG3

pro_dcache_dbug4: Reg<PRO_DCACHE_DBUG4_SPEC>

0x400 - DPORT_PRO_DCACHE_DBUG4

pro_dcache_dbug5: Reg<PRO_DCACHE_DBUG5_SPEC>

0x404 - DPORT_PRO_DCACHE_DBUG5

pro_dcache_dbug6: Reg<PRO_DCACHE_DBUG6_SPEC>

0x408 - DPORT_PRO_DCACHE_DBUG6

pro_dcache_dbug7: Reg<PRO_DCACHE_DBUG7_SPEC>

0x40c - DPORT_PRO_DCACHE_DBUG7

pro_dcache_dbug8: Reg<PRO_DCACHE_DBUG8_SPEC>

0x410 - DPORT_PRO_DCACHE_DBUG8

pro_dcache_dbug9: Reg<PRO_DCACHE_DBUG9_SPEC>

0x414 - DPORT_PRO_DCACHE_DBUG9

app_dcache_dbug0: Reg<APP_DCACHE_DBUG0_SPEC>

0x418 - DPORT_APP_DCACHE_DBUG0

app_dcache_dbug1: Reg<APP_DCACHE_DBUG1_SPEC>

0x41c - DPORT_APP_DCACHE_DBUG1

app_dcache_dbug2: Reg<APP_DCACHE_DBUG2_SPEC>

0x420 - DPORT_APP_DCACHE_DBUG2

app_dcache_dbug3: Reg<APP_DCACHE_DBUG3_SPEC>

0x424 - DPORT_APP_DCACHE_DBUG3

app_dcache_dbug4: Reg<APP_DCACHE_DBUG4_SPEC>

0x428 - DPORT_APP_DCACHE_DBUG4

app_dcache_dbug5: Reg<APP_DCACHE_DBUG5_SPEC>

0x42c - DPORT_APP_DCACHE_DBUG5

app_dcache_dbug6: Reg<APP_DCACHE_DBUG6_SPEC>

0x430 - DPORT_APP_DCACHE_DBUG6

app_dcache_dbug7: Reg<APP_DCACHE_DBUG7_SPEC>

0x434 - DPORT_APP_DCACHE_DBUG7

app_dcache_dbug8: Reg<APP_DCACHE_DBUG8_SPEC>

0x438 - DPORT_APP_DCACHE_DBUG8

app_dcache_dbug9: Reg<APP_DCACHE_DBUG9_SPEC>

0x43c - DPORT_APP_DCACHE_DBUG9

pro_cpu_record_ctrl: Reg<PRO_CPU_RECORD_CTRL_SPEC>

0x440 - DPORT_PRO_CPU_RECORD_CTRL

pro_cpu_record_status: Reg<PRO_CPU_RECORD_STATUS_SPEC>

0x444 - DPORT_PRO_CPU_RECORD_STATUS

pro_cpu_record_pid: Reg<PRO_CPU_RECORD_PID_SPEC>

0x448 - DPORT_PRO_CPU_RECORD_PID

pro_cpu_record_pdebuginst: Reg<PRO_CPU_RECORD_PDEBUGINST_SPEC>

0x44c - DPORT_PRO_CPU_RECORD_PDEBUGINST

pro_cpu_record_pdebugstatus: Reg<PRO_CPU_RECORD_PDEBUGSTATUS_SPEC>

0x450 - DPORT_PRO_CPU_RECORD_PDEBUGSTATUS

pro_cpu_record_pdebugdata: Reg<PRO_CPU_RECORD_PDEBUGDATA_SPEC>

0x454 - DPORT_PRO_CPU_RECORD_PDEBUGDATA

pro_cpu_record_pdebugpc: Reg<PRO_CPU_RECORD_PDEBUGPC_SPEC>

0x458 - DPORT_PRO_CPU_RECORD_PDEBUGPC

pro_cpu_record_pdebugls0stat: Reg<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC>

0x45c - DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT

pro_cpu_record_pdebugls0addr: Reg<PRO_CPU_RECORD_PDEBUGLS0ADDR_SPEC>

0x460 - DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR

pro_cpu_record_pdebugls0data: Reg<PRO_CPU_RECORD_PDEBUGLS0DATA_SPEC>

0x464 - DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA

app_cpu_record_ctrl: Reg<APP_CPU_RECORD_CTRL_SPEC>

0x468 - DPORT_APP_CPU_RECORD_CTRL

app_cpu_record_status: Reg<APP_CPU_RECORD_STATUS_SPEC>

0x46c - DPORT_APP_CPU_RECORD_STATUS

app_cpu_record_pid: Reg<APP_CPU_RECORD_PID_SPEC>

0x470 - DPORT_APP_CPU_RECORD_PID

app_cpu_record_pdebuginst: Reg<APP_CPU_RECORD_PDEBUGINST_SPEC>

0x474 - DPORT_APP_CPU_RECORD_PDEBUGINST

app_cpu_record_pdebugstatus: Reg<APP_CPU_RECORD_PDEBUGSTATUS_SPEC>

0x478 - DPORT_APP_CPU_RECORD_PDEBUGSTATUS

app_cpu_record_pdebugdata: Reg<APP_CPU_RECORD_PDEBUGDATA_SPEC>

0x47c - DPORT_APP_CPU_RECORD_PDEBUGDATA

app_cpu_record_pdebugpc: Reg<APP_CPU_RECORD_PDEBUGPC_SPEC>

0x480 - DPORT_APP_CPU_RECORD_PDEBUGPC

app_cpu_record_pdebugls0stat: Reg<APP_CPU_RECORD_PDEBUGLS0STAT_SPEC>

0x484 - DPORT_APP_CPU_RECORD_PDEBUGLS0STAT

app_cpu_record_pdebugls0addr: Reg<APP_CPU_RECORD_PDEBUGLS0ADDR_SPEC>

0x488 - DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR

app_cpu_record_pdebugls0data: Reg<APP_CPU_RECORD_PDEBUGLS0DATA_SPEC>

0x48c - DPORT_APP_CPU_RECORD_PDEBUGLS0DATA

rsa_pd_ctrl: Reg<RSA_PD_CTRL_SPEC>

0x490 - DPORT_RSA_PD_CTRL

rom_mpu_table0: Reg<ROM_MPU_TABLE0_SPEC>

0x494 - DPORT_ROM_MPU_TABLE0

rom_mpu_table1: Reg<ROM_MPU_TABLE1_SPEC>

0x498 - DPORT_ROM_MPU_TABLE1

rom_mpu_table2: Reg<ROM_MPU_TABLE2_SPEC>

0x49c - DPORT_ROM_MPU_TABLE2

rom_mpu_table3: Reg<ROM_MPU_TABLE3_SPEC>

0x4a0 - DPORT_ROM_MPU_TABLE3

shrom_mpu_table0: Reg<SHROM_MPU_TABLE0_SPEC>

0x4a4 - DPORT_SHROM_MPU_TABLE0

shrom_mpu_table1: Reg<SHROM_MPU_TABLE1_SPEC>

0x4a8 - DPORT_SHROM_MPU_TABLE1

shrom_mpu_table2: Reg<SHROM_MPU_TABLE2_SPEC>

0x4ac - DPORT_SHROM_MPU_TABLE2

shrom_mpu_table3: Reg<SHROM_MPU_TABLE3_SPEC>

0x4b0 - DPORT_SHROM_MPU_TABLE3

shrom_mpu_table4: Reg<SHROM_MPU_TABLE4_SPEC>

0x4b4 - DPORT_SHROM_MPU_TABLE4

shrom_mpu_table5: Reg<SHROM_MPU_TABLE5_SPEC>

0x4b8 - DPORT_SHROM_MPU_TABLE5

shrom_mpu_table6: Reg<SHROM_MPU_TABLE6_SPEC>

0x4bc - DPORT_SHROM_MPU_TABLE6

shrom_mpu_table7: Reg<SHROM_MPU_TABLE7_SPEC>

0x4c0 - DPORT_SHROM_MPU_TABLE7

shrom_mpu_table8: Reg<SHROM_MPU_TABLE8_SPEC>

0x4c4 - DPORT_SHROM_MPU_TABLE8

shrom_mpu_table9: Reg<SHROM_MPU_TABLE9_SPEC>

0x4c8 - DPORT_SHROM_MPU_TABLE9

shrom_mpu_table10: Reg<SHROM_MPU_TABLE10_SPEC>

0x4cc - DPORT_SHROM_MPU_TABLE10

shrom_mpu_table11: Reg<SHROM_MPU_TABLE11_SPEC>

0x4d0 - DPORT_SHROM_MPU_TABLE11

shrom_mpu_table12: Reg<SHROM_MPU_TABLE12_SPEC>

0x4d4 - DPORT_SHROM_MPU_TABLE12

shrom_mpu_table13: Reg<SHROM_MPU_TABLE13_SPEC>

0x4d8 - DPORT_SHROM_MPU_TABLE13

shrom_mpu_table14: Reg<SHROM_MPU_TABLE14_SPEC>

0x4dc - DPORT_SHROM_MPU_TABLE14

shrom_mpu_table15: Reg<SHROM_MPU_TABLE15_SPEC>

0x4e0 - DPORT_SHROM_MPU_TABLE15

shrom_mpu_table16: Reg<SHROM_MPU_TABLE16_SPEC>

0x4e4 - DPORT_SHROM_MPU_TABLE16

shrom_mpu_table17: Reg<SHROM_MPU_TABLE17_SPEC>

0x4e8 - DPORT_SHROM_MPU_TABLE17

shrom_mpu_table18: Reg<SHROM_MPU_TABLE18_SPEC>

0x4ec - DPORT_SHROM_MPU_TABLE18

shrom_mpu_table19: Reg<SHROM_MPU_TABLE19_SPEC>

0x4f0 - DPORT_SHROM_MPU_TABLE19

shrom_mpu_table20: Reg<SHROM_MPU_TABLE20_SPEC>

0x4f4 - DPORT_SHROM_MPU_TABLE20

shrom_mpu_table21: Reg<SHROM_MPU_TABLE21_SPEC>

0x4f8 - DPORT_SHROM_MPU_TABLE21

shrom_mpu_table22: Reg<SHROM_MPU_TABLE22_SPEC>

0x4fc - DPORT_SHROM_MPU_TABLE22

shrom_mpu_table23: Reg<SHROM_MPU_TABLE23_SPEC>

0x500 - DPORT_SHROM_MPU_TABLE23

immu_table0: Reg<IMMU_TABLE0_SPEC>

0x504 - DPORT_IMMU_TABLE0

immu_table1: Reg<IMMU_TABLE1_SPEC>

0x508 - DPORT_IMMU_TABLE1

immu_table2: Reg<IMMU_TABLE2_SPEC>

0x50c - DPORT_IMMU_TABLE2

immu_table3: Reg<IMMU_TABLE3_SPEC>

0x510 - DPORT_IMMU_TABLE3

immu_table4: Reg<IMMU_TABLE4_SPEC>

0x514 - DPORT_IMMU_TABLE4

immu_table5: Reg<IMMU_TABLE5_SPEC>

0x518 - DPORT_IMMU_TABLE5

immu_table6: Reg<IMMU_TABLE6_SPEC>

0x51c - DPORT_IMMU_TABLE6

immu_table7: Reg<IMMU_TABLE7_SPEC>

0x520 - DPORT_IMMU_TABLE7

immu_table8: Reg<IMMU_TABLE8_SPEC>

0x524 - DPORT_IMMU_TABLE8

immu_table9: Reg<IMMU_TABLE9_SPEC>

0x528 - DPORT_IMMU_TABLE9

immu_table10: Reg<IMMU_TABLE10_SPEC>

0x52c - DPORT_IMMU_TABLE10

immu_table11: Reg<IMMU_TABLE11_SPEC>

0x530 - DPORT_IMMU_TABLE11

immu_table12: Reg<IMMU_TABLE12_SPEC>

0x534 - DPORT_IMMU_TABLE12

immu_table13: Reg<IMMU_TABLE13_SPEC>

0x538 - DPORT_IMMU_TABLE13

immu_table14: Reg<IMMU_TABLE14_SPEC>

0x53c - DPORT_IMMU_TABLE14

immu_table15: Reg<IMMU_TABLE15_SPEC>

0x540 - DPORT_IMMU_TABLE15

dmmu_table0: Reg<DMMU_TABLE0_SPEC>

0x544 - DPORT_DMMU_TABLE0

dmmu_table1: Reg<DMMU_TABLE1_SPEC>

0x548 - DPORT_DMMU_TABLE1

dmmu_table2: Reg<DMMU_TABLE2_SPEC>

0x54c - DPORT_DMMU_TABLE2

dmmu_table3: Reg<DMMU_TABLE3_SPEC>

0x550 - DPORT_DMMU_TABLE3

dmmu_table4: Reg<DMMU_TABLE4_SPEC>

0x554 - DPORT_DMMU_TABLE4

dmmu_table5: Reg<DMMU_TABLE5_SPEC>

0x558 - DPORT_DMMU_TABLE5

dmmu_table6: Reg<DMMU_TABLE6_SPEC>

0x55c - DPORT_DMMU_TABLE6

dmmu_table7: Reg<DMMU_TABLE7_SPEC>

0x560 - DPORT_DMMU_TABLE7

dmmu_table8: Reg<DMMU_TABLE8_SPEC>

0x564 - DPORT_DMMU_TABLE8

dmmu_table9: Reg<DMMU_TABLE9_SPEC>

0x568 - DPORT_DMMU_TABLE9

dmmu_table10: Reg<DMMU_TABLE10_SPEC>

0x56c - DPORT_DMMU_TABLE10

dmmu_table11: Reg<DMMU_TABLE11_SPEC>

0x570 - DPORT_DMMU_TABLE11

dmmu_table12: Reg<DMMU_TABLE12_SPEC>

0x574 - DPORT_DMMU_TABLE12

dmmu_table13: Reg<DMMU_TABLE13_SPEC>

0x578 - DPORT_DMMU_TABLE13

dmmu_table14: Reg<DMMU_TABLE14_SPEC>

0x57c - DPORT_DMMU_TABLE14

dmmu_table15: Reg<DMMU_TABLE15_SPEC>

0x580 - DPORT_DMMU_TABLE15

pro_intrusion_ctrl: Reg<PRO_INTRUSION_CTRL_SPEC>

0x584 - DPORT_PRO_INTRUSION_CTRL

pro_intrusion_status: Reg<PRO_INTRUSION_STATUS_SPEC>

0x588 - DPORT_PRO_INTRUSION_STATUS

app_intrusion_ctrl: Reg<APP_INTRUSION_CTRL_SPEC>

0x58c - DPORT_APP_INTRUSION_CTRL

app_intrusion_status: Reg<APP_INTRUSION_STATUS_SPEC>

0x590 - DPORT_APP_INTRUSION_STATUS

front_end_mem_pd: Reg<FRONT_END_MEM_PD_SPEC>

0x594 - DPORT_FRONT_END_MEM_PD

mmu_ia_int_en: Reg<MMU_IA_INT_EN_SPEC>

0x598 - DPORT_MMU_IA_INT_EN

mpu_ia_int_en: Reg<MPU_IA_INT_EN_SPEC>

0x59c - DPORT_MPU_IA_INT_EN

cache_ia_int_en: Reg<CACHE_IA_INT_EN_SPEC>

0x5a0 - DPORT_CACHE_IA_INT_EN

secure_boot_ctrl: Reg<SECURE_BOOT_CTRL_SPEC>

0x5a4 - DPORT_SECURE_BOOT_CTRL

spi_dma_chan_sel: Reg<SPI_DMA_CHAN_SEL_SPEC>

0x5a8 - DPORT_SPI_DMA_CHAN_SEL

pro_vecbase_ctrl: Reg<PRO_VECBASE_CTRL_SPEC>

0x5ac - DPORT_PRO_VECBASE_CTRL

pro_vecbase_set: Reg<PRO_VECBASE_SET_SPEC>

0x5b0 - DPORT_PRO_VECBASE_SET

app_vecbase_ctrl: Reg<APP_VECBASE_CTRL_SPEC>

0x5b4 - DPORT_APP_VECBASE_CTRL

app_vecbase_set: Reg<APP_VECBASE_SET_SPEC>

0x5b8 - DPORT_APP_VECBASE_SET

date: Reg<DATE_SPEC>

0xffc - DPORT_DATE