Struct esp32::dport::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub dport_pro_boot_remap_ctrl_reg: DPORT_PRO_BOOT_REMAP_CTRL_REG,
    pub dport_app_boot_remap_ctrl_reg: DPORT_APP_BOOT_REMAP_CTRL_REG,
    pub dport_access_check_reg: DPORT_ACCESS_CHECK_REG,
    pub dport_pro_dport_apb_mask0_reg: DPORT_PRO_DPORT_APB_MASK0_REG,
    pub dport_pro_dport_apb_mask1_reg: DPORT_PRO_DPORT_APB_MASK1_REG,
    pub dport_app_dport_apb_mask0_reg: DPORT_APP_DPORT_APB_MASK0_REG,
    pub dport_app_dport_apb_mask1_reg: DPORT_APP_DPORT_APB_MASK1_REG,
    pub dport_peri_clk_en_reg: DPORT_PERI_CLK_EN_REG,
    pub dport_peri_rst_en_reg: DPORT_PERI_RST_EN_REG,
    pub dport_wifi_bb_cfg_reg: DPORT_WIFI_BB_CFG_REG,
    pub dport_wifi_bb_cfg_2_reg: DPORT_WIFI_BB_CFG_2_REG,
    pub dport_appcpu_ctrl_a_reg: DPORT_APPCPU_CTRL_A_REG,
    pub dport_appcpu_ctrl_b_reg: DPORT_APPCPU_CTRL_B_REG,
    pub dport_appcpu_ctrl_c_reg: DPORT_APPCPU_CTRL_C_REG,
    pub dport_appcpu_ctrl_d_reg: DPORT_APPCPU_CTRL_D_REG,
    pub dport_cpu_per_conf_reg: DPORT_CPU_PER_CONF_REG,
    pub dport_pro_cache_ctrl_reg: DPORT_PRO_CACHE_CTRL_REG,
    pub dport_pro_cache_ctrl1_reg: DPORT_PRO_CACHE_CTRL1_REG,
    pub dport_pro_cache_lock_0_addr_reg: DPORT_PRO_CACHE_LOCK_0_ADDR_REG,
    pub dport_pro_cache_lock_1_addr_reg: DPORT_PRO_CACHE_LOCK_1_ADDR_REG,
    pub dport_pro_cache_lock_2_addr_reg: DPORT_PRO_CACHE_LOCK_2_ADDR_REG,
    pub dport_pro_cache_lock_3_addr_reg: DPORT_PRO_CACHE_LOCK_3_ADDR_REG,
    pub dport_app_cache_ctrl_reg: DPORT_APP_CACHE_CTRL_REG,
    pub dport_app_cache_ctrl1_reg: DPORT_APP_CACHE_CTRL1_REG,
    pub dport_app_cache_lock_0_addr_reg: DPORT_APP_CACHE_LOCK_0_ADDR_REG,
    pub dport_app_cache_lock_1_addr_reg: DPORT_APP_CACHE_LOCK_1_ADDR_REG,
    pub dport_app_cache_lock_2_addr_reg: DPORT_APP_CACHE_LOCK_2_ADDR_REG,
    pub dport_app_cache_lock_3_addr_reg: DPORT_APP_CACHE_LOCK_3_ADDR_REG,
    pub dport_tracemem_mux_mode_reg: DPORT_TRACEMEM_MUX_MODE_REG,
    pub dport_pro_tracemem_ena_reg: DPORT_PRO_TRACEMEM_ENA_REG,
    pub dport_app_tracemem_ena_reg: DPORT_APP_TRACEMEM_ENA_REG,
    pub dport_cache_mux_mode_reg: DPORT_CACHE_MUX_MODE_REG,
    pub dport_immu_page_mode_reg: DPORT_IMMU_PAGE_MODE_REG,
    pub dport_dmmu_page_mode_reg: DPORT_DMMU_PAGE_MODE_REG,
    pub dport_rom_mpu_ena_reg: DPORT_ROM_MPU_ENA_REG,
    pub dport_mem_pd_mask_reg: DPORT_MEM_PD_MASK_REG,
    pub dport_rom_pd_ctrl_reg: DPORT_ROM_PD_CTRL_REG,
    pub dport_rom_fo_ctrl_reg: DPORT_ROM_FO_CTRL_REG,
    pub dport_sram_pd_ctrl_0_reg: DPORT_SRAM_PD_CTRL_0_REG,
    pub dport_sram_pd_ctrl_1_reg: DPORT_SRAM_PD_CTRL_1_REG,
    pub dport_sram_fo_ctrl_0_reg: DPORT_SRAM_FO_CTRL_0_REG,
    pub dport_sram_fo_ctrl_1_reg: DPORT_SRAM_FO_CTRL_1_REG,
    pub dport_iram_dram_ahb_sel_reg: DPORT_IRAM_DRAM_AHB_SEL_REG,
    pub dport_tag_fo_ctrl_reg: DPORT_TAG_FO_CTRL_REG,
    pub dport_ahb_lite_mask_reg: DPORT_AHB_LITE_MASK_REG,
    pub dport_ahb_mpu_table_0_reg: DPORT_AHB_MPU_TABLE_0_REG,
    pub dport_ahb_mpu_table_1_reg: DPORT_AHB_MPU_TABLE_1_REG,
    pub dport_host_inf_sel_reg: DPORT_HOST_INF_SEL_REG,
    pub dport_perip_clk_en_reg: DPORT_PERIP_CLK_EN_REG,
    pub dport_perip_rst_en_reg: DPORT_PERIP_RST_EN_REG,
    pub dport_wifi_clk_en_reg: DPORT_WIFI_CLK_EN_REG,
    pub dport_core_rst_en_reg: DPORT_CORE_RST_EN_REG,
    pub dport_bt_lpck_div_int_reg: DPORT_BT_LPCK_DIV_INT_REG,
    pub dport_bt_lpck_div_frac_reg: DPORT_BT_LPCK_DIV_FRAC_REG,
    pub dport_cpu_intr_from_cpu_0_reg: DPORT_CPU_INTR_FROM_CPU_0_REG,
    pub dport_cpu_intr_from_cpu_1_reg: DPORT_CPU_INTR_FROM_CPU_1_REG,
    pub dport_cpu_intr_from_cpu_2_reg: DPORT_CPU_INTR_FROM_CPU_2_REG,
    pub dport_cpu_intr_from_cpu_3_reg: DPORT_CPU_INTR_FROM_CPU_3_REG,
    pub dport_pro_intr_status_0_reg: DPORT_PRO_INTR_STATUS_0_REG,
    pub dport_pro_intr_status_1_reg: DPORT_PRO_INTR_STATUS_1_REG,
    pub dport_pro_intr_status_2_reg: DPORT_PRO_INTR_STATUS_2_REG,
    pub dport_app_intr_status_0_reg: DPORT_APP_INTR_STATUS_0_REG,
    pub dport_app_intr_status_1_reg: DPORT_APP_INTR_STATUS_1_REG,
    pub dport_app_intr_status_2_reg: DPORT_APP_INTR_STATUS_2_REG,
    pub dport_pro_mac_intr_map_reg: DPORT_PRO_MAC_INTR_MAP_REG,
    pub dport_pro_mac_nmi_map_reg: DPORT_PRO_MAC_NMI_MAP_REG,
    pub dport_pro_bb_int_map_reg: DPORT_PRO_BB_INT_MAP_REG,
    pub dport_pro_bt_mac_int_map_reg: DPORT_PRO_BT_MAC_INT_MAP_REG,
    pub dport_pro_bt_bb_int_map_reg: DPORT_PRO_BT_BB_INT_MAP_REG,
    pub dport_pro_bt_bb_nmi_map_reg: DPORT_PRO_BT_BB_NMI_MAP_REG,
    pub dport_pro_rwbt_irq_map_reg: DPORT_PRO_RWBT_IRQ_MAP_REG,
    pub dport_pro_rwble_irq_map_reg: DPORT_PRO_RWBLE_IRQ_MAP_REG,
    pub dport_pro_rwbt_nmi_map_reg: DPORT_PRO_RWBT_NMI_MAP_REG,
    pub dport_pro_rwble_nmi_map_reg: DPORT_PRO_RWBLE_NMI_MAP_REG,
    pub dport_pro_slc0_intr_map_reg: DPORT_PRO_SLC0_INTR_MAP_REG,
    pub dport_pro_slc1_intr_map_reg: DPORT_PRO_SLC1_INTR_MAP_REG,
    pub dport_pro_uhci0_intr_map_reg: DPORT_PRO_UHCI0_INTR_MAP_REG,
    pub dport_pro_uhci1_intr_map_reg: DPORT_PRO_UHCI1_INTR_MAP_REG,
    pub dport_pro_tg_t0_level_int_map_reg: DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG,
    pub dport_pro_tg_t1_level_int_map_reg: DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG,
    pub dport_pro_tg_wdt_level_int_map_reg: DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG,
    pub dport_pro_tg_lact_level_int_map_reg: DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG,
    pub dport_pro_tg1_t0_level_int_map_reg: DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG,
    pub dport_pro_tg1_t1_level_int_map_reg: DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG,
    pub dport_pro_tg1_wdt_level_int_map_reg: DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG,
    pub dport_pro_tg1_lact_level_int_map_reg: DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG,
    pub dport_pro_gpio_interrupt_map_reg: DPORT_PRO_GPIO_INTERRUPT_MAP_REG,
    pub dport_pro_gpio_interrupt_nmi_map_reg: DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG,
    pub dport_pro_cpu_intr_from_cpu_0_map_reg: DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG,
    pub dport_pro_cpu_intr_from_cpu_1_map_reg: DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG,
    pub dport_pro_cpu_intr_from_cpu_2_map_reg: DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG,
    pub dport_pro_cpu_intr_from_cpu_3_map_reg: DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG,
    pub dport_pro_spi_intr_0_map_reg: DPORT_PRO_SPI_INTR_0_MAP_REG,
    pub dport_pro_spi_intr_1_map_reg: DPORT_PRO_SPI_INTR_1_MAP_REG,
    pub dport_pro_spi_intr_2_map_reg: DPORT_PRO_SPI_INTR_2_MAP_REG,
    pub dport_pro_spi_intr_3_map_reg: DPORT_PRO_SPI_INTR_3_MAP_REG,
    pub dport_pro_i2s0_int_map_reg: DPORT_PRO_I2S0_INT_MAP_REG,
    pub dport_pro_i2s1_int_map_reg: DPORT_PRO_I2S1_INT_MAP_REG,
    pub dport_pro_uart_intr_map_reg: DPORT_PRO_UART_INTR_MAP_REG,
    pub dport_pro_uart1_intr_map_reg: DPORT_PRO_UART1_INTR_MAP_REG,
    pub dport_pro_uart2_intr_map_reg: DPORT_PRO_UART2_INTR_MAP_REG,
    pub dport_pro_sdio_host_interrupt_map_reg: DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG,
    pub dport_pro_emac_int_map_reg: DPORT_PRO_EMAC_INT_MAP_REG,
    pub dport_pro_pwm0_intr_map_reg: DPORT_PRO_PWM0_INTR_MAP_REG,
    pub dport_pro_pwm1_intr_map_reg: DPORT_PRO_PWM1_INTR_MAP_REG,
    pub dport_pro_pwm2_intr_map_reg: DPORT_PRO_PWM2_INTR_MAP_REG,
    pub dport_pro_pwm3_intr_map_reg: DPORT_PRO_PWM3_INTR_MAP_REG,
    pub dport_pro_ledc_int_map_reg: DPORT_PRO_LEDC_INT_MAP_REG,
    pub dport_pro_efuse_int_map_reg: DPORT_PRO_EFUSE_INT_MAP_REG,
    pub dport_pro_can_int_map_reg: DPORT_PRO_CAN_INT_MAP_REG,
    pub dport_pro_rtc_core_intr_map_reg: DPORT_PRO_RTC_CORE_INTR_MAP_REG,
    pub dport_pro_rmt_intr_map_reg: DPORT_PRO_RMT_INTR_MAP_REG,
    pub dport_pro_pcnt_intr_map_reg: DPORT_PRO_PCNT_INTR_MAP_REG,
    pub dport_pro_i2c_ext0_intr_map_reg: DPORT_PRO_I2C_EXT0_INTR_MAP_REG,
    pub dport_pro_i2c_ext1_intr_map_reg: DPORT_PRO_I2C_EXT1_INTR_MAP_REG,
    pub dport_pro_rsa_intr_map_reg: DPORT_PRO_RSA_INTR_MAP_REG,
    pub dport_pro_spi1_dma_int_map_reg: DPORT_PRO_SPI1_DMA_INT_MAP_REG,
    pub dport_pro_spi2_dma_int_map_reg: DPORT_PRO_SPI2_DMA_INT_MAP_REG,
    pub dport_pro_spi3_dma_int_map_reg: DPORT_PRO_SPI3_DMA_INT_MAP_REG,
    pub dport_pro_wdg_int_map_reg: DPORT_PRO_WDG_INT_MAP_REG,
    pub dport_pro_timer_int1_map_reg: DPORT_PRO_TIMER_INT1_MAP_REG,
    pub dport_pro_timer_int2_map_reg: DPORT_PRO_TIMER_INT2_MAP_REG,
    pub dport_pro_tg_t0_edge_int_map_reg: DPORT_PRO_TG_T0_EDGE_INT_MAP_REG,
    pub dport_pro_tg_t1_edge_int_map_reg: DPORT_PRO_TG_T1_EDGE_INT_MAP_REG,
    pub dport_pro_tg_wdt_edge_int_map_reg: DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG,
    pub dport_pro_tg_lact_edge_int_map_reg: DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG,
    pub dport_pro_tg1_t0_edge_int_map_reg: DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG,
    pub dport_pro_tg1_t1_edge_int_map_reg: DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG,
    pub dport_pro_tg1_wdt_edge_int_map_reg: DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG,
    pub dport_pro_tg1_lact_edge_int_map_reg: DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG,
    pub dport_pro_mmu_ia_int_map_reg: DPORT_PRO_MMU_IA_INT_MAP_REG,
    pub dport_pro_mpu_ia_int_map_reg: DPORT_PRO_MPU_IA_INT_MAP_REG,
    pub dport_pro_cache_ia_int_map_reg: DPORT_PRO_CACHE_IA_INT_MAP_REG,
    pub dport_app_mac_intr_map_reg: DPORT_APP_MAC_INTR_MAP_REG,
    pub dport_app_mac_nmi_map_reg: DPORT_APP_MAC_NMI_MAP_REG,
    pub dport_app_bb_int_map_reg: DPORT_APP_BB_INT_MAP_REG,
    pub dport_app_bt_mac_int_map_reg: DPORT_APP_BT_MAC_INT_MAP_REG,
    pub dport_app_bt_bb_int_map_reg: DPORT_APP_BT_BB_INT_MAP_REG,
    pub dport_app_bt_bb_nmi_map_reg: DPORT_APP_BT_BB_NMI_MAP_REG,
    pub dport_app_rwbt_irq_map_reg: DPORT_APP_RWBT_IRQ_MAP_REG,
    pub dport_app_rwble_irq_map_reg: DPORT_APP_RWBLE_IRQ_MAP_REG,
    pub dport_app_rwbt_nmi_map_reg: DPORT_APP_RWBT_NMI_MAP_REG,
    pub dport_app_rwble_nmi_map_reg: DPORT_APP_RWBLE_NMI_MAP_REG,
    pub dport_app_slc0_intr_map_reg: DPORT_APP_SLC0_INTR_MAP_REG,
    pub dport_app_slc1_intr_map_reg: DPORT_APP_SLC1_INTR_MAP_REG,
    pub dport_app_uhci0_intr_map_reg: DPORT_APP_UHCI0_INTR_MAP_REG,
    pub dport_app_uhci1_intr_map_reg: DPORT_APP_UHCI1_INTR_MAP_REG,
    pub dport_app_tg_t0_level_int_map_reg: DPORT_APP_TG_T0_LEVEL_INT_MAP_REG,
    pub dport_app_tg_t1_level_int_map_reg: DPORT_APP_TG_T1_LEVEL_INT_MAP_REG,
    pub dport_app_tg_wdt_level_int_map_reg: DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG,
    pub dport_app_tg_lact_level_int_map_reg: DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG,
    pub dport_app_tg1_t0_level_int_map_reg: DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG,
    pub dport_app_tg1_t1_level_int_map_reg: DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG,
    pub dport_app_tg1_wdt_level_int_map_reg: DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG,
    pub dport_app_tg1_lact_level_int_map_reg: DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG,
    pub dport_app_gpio_interrupt_map_reg: DPORT_APP_GPIO_INTERRUPT_MAP_REG,
    pub dport_app_gpio_interrupt_nmi_map_reg: DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG,
    pub dport_app_cpu_intr_from_cpu_0_map_reg: DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG,
    pub dport_app_cpu_intr_from_cpu_1_map_reg: DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG,
    pub dport_app_cpu_intr_from_cpu_2_map_reg: DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG,
    pub dport_app_cpu_intr_from_cpu_3_map_reg: DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG,
    pub dport_app_spi_intr_0_map_reg: DPORT_APP_SPI_INTR_0_MAP_REG,
    pub dport_app_spi_intr_1_map_reg: DPORT_APP_SPI_INTR_1_MAP_REG,
    pub dport_app_spi_intr_2_map_reg: DPORT_APP_SPI_INTR_2_MAP_REG,
    pub dport_app_spi_intr_3_map_reg: DPORT_APP_SPI_INTR_3_MAP_REG,
    pub dport_app_i2s0_int_map_reg: DPORT_APP_I2S0_INT_MAP_REG,
    pub dport_app_i2s1_int_map_reg: DPORT_APP_I2S1_INT_MAP_REG,
    pub dport_app_uart_intr_map_reg: DPORT_APP_UART_INTR_MAP_REG,
    pub dport_app_uart1_intr_map_reg: DPORT_APP_UART1_INTR_MAP_REG,
    pub dport_app_uart2_intr_map_reg: DPORT_APP_UART2_INTR_MAP_REG,
    pub dport_app_sdio_host_interrupt_map_reg: DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG,
    pub dport_app_emac_int_map_reg: DPORT_APP_EMAC_INT_MAP_REG,
    pub dport_app_pwm0_intr_map_reg: DPORT_APP_PWM0_INTR_MAP_REG,
    pub dport_app_pwm1_intr_map_reg: DPORT_APP_PWM1_INTR_MAP_REG,
    pub dport_app_pwm2_intr_map_reg: DPORT_APP_PWM2_INTR_MAP_REG,
    pub dport_app_pwm3_intr_map_reg: DPORT_APP_PWM3_INTR_MAP_REG,
    pub dport_app_ledc_int_map_reg: DPORT_APP_LEDC_INT_MAP_REG,
    pub dport_app_efuse_int_map_reg: DPORT_APP_EFUSE_INT_MAP_REG,
    pub dport_app_can_int_map_reg: DPORT_APP_CAN_INT_MAP_REG,
    pub dport_app_rtc_core_intr_map_reg: DPORT_APP_RTC_CORE_INTR_MAP_REG,
    pub dport_app_rmt_intr_map_reg: DPORT_APP_RMT_INTR_MAP_REG,
    pub dport_app_pcnt_intr_map_reg: DPORT_APP_PCNT_INTR_MAP_REG,
    pub dport_app_i2c_ext0_intr_map_reg: DPORT_APP_I2C_EXT0_INTR_MAP_REG,
    pub dport_app_i2c_ext1_intr_map_reg: DPORT_APP_I2C_EXT1_INTR_MAP_REG,
    pub dport_app_rsa_intr_map_reg: DPORT_APP_RSA_INTR_MAP_REG,
    pub dport_app_spi1_dma_int_map_reg: DPORT_APP_SPI1_DMA_INT_MAP_REG,
    pub dport_app_spi2_dma_int_map_reg: DPORT_APP_SPI2_DMA_INT_MAP_REG,
    pub dport_app_spi3_dma_int_map_reg: DPORT_APP_SPI3_DMA_INT_MAP_REG,
    pub dport_app_wdg_int_map_reg: DPORT_APP_WDG_INT_MAP_REG,
    pub dport_app_timer_int1_map_reg: DPORT_APP_TIMER_INT1_MAP_REG,
    pub dport_app_timer_int2_map_reg: DPORT_APP_TIMER_INT2_MAP_REG,
    pub dport_app_tg_t0_edge_int_map_reg: DPORT_APP_TG_T0_EDGE_INT_MAP_REG,
    pub dport_app_tg_t1_edge_int_map_reg: DPORT_APP_TG_T1_EDGE_INT_MAP_REG,
    pub dport_app_tg_wdt_edge_int_map_reg: DPORT_APP_TG_WDT_EDGE_INT_MAP_REG,
    pub dport_app_tg_lact_edge_int_map_reg: DPORT_APP_TG_LACT_EDGE_INT_MAP_REG,
    pub dport_app_tg1_t0_edge_int_map_reg: DPORT_APP_TG1_T0_EDGE_INT_MAP_REG,
    pub dport_app_tg1_t1_edge_int_map_reg: DPORT_APP_TG1_T1_EDGE_INT_MAP_REG,
    pub dport_app_tg1_wdt_edge_int_map_reg: DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG,
    pub dport_app_tg1_lact_edge_int_map_reg: DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG,
    pub dport_app_mmu_ia_int_map_reg: DPORT_APP_MMU_IA_INT_MAP_REG,
    pub dport_app_mpu_ia_int_map_reg: DPORT_APP_MPU_IA_INT_MAP_REG,
    pub dport_app_cache_ia_int_map_reg: DPORT_APP_CACHE_IA_INT_MAP_REG,
    pub dport_ahblite_mpu_table_uart_reg: DPORT_AHBLITE_MPU_TABLE_UART_REG,
    pub dport_ahblite_mpu_table_spi1_reg: DPORT_AHBLITE_MPU_TABLE_SPI1_REG,
    pub dport_ahblite_mpu_table_spi0_reg: DPORT_AHBLITE_MPU_TABLE_SPI0_REG,
    pub dport_ahblite_mpu_table_gpio_reg: DPORT_AHBLITE_MPU_TABLE_GPIO_REG,
    pub dport_ahblite_mpu_table_fe2_reg: DPORT_AHBLITE_MPU_TABLE_FE2_REG,
    pub dport_ahblite_mpu_table_fe_reg: DPORT_AHBLITE_MPU_TABLE_FE_REG,
    pub dport_ahblite_mpu_table_timer_reg: DPORT_AHBLITE_MPU_TABLE_TIMER_REG,
    pub dport_ahblite_mpu_table_rtc_reg: DPORT_AHBLITE_MPU_TABLE_RTC_REG,
    pub dport_ahblite_mpu_table_io_mux_reg: DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG,
    pub dport_ahblite_mpu_table_wdg_reg: DPORT_AHBLITE_MPU_TABLE_WDG_REG,
    pub dport_ahblite_mpu_table_hinf_reg: DPORT_AHBLITE_MPU_TABLE_HINF_REG,
    pub dport_ahblite_mpu_table_uhci1_reg: DPORT_AHBLITE_MPU_TABLE_UHCI1_REG,
    pub dport_ahblite_mpu_table_misc_reg: DPORT_AHBLITE_MPU_TABLE_MISC_REG,
    pub dport_ahblite_mpu_table_i2c_reg: DPORT_AHBLITE_MPU_TABLE_I2C_REG,
    pub dport_ahblite_mpu_table_i2s0_reg: DPORT_AHBLITE_MPU_TABLE_I2S0_REG,
    pub dport_ahblite_mpu_table_uart1_reg: DPORT_AHBLITE_MPU_TABLE_UART1_REG,
    pub dport_ahblite_mpu_table_bt_reg: DPORT_AHBLITE_MPU_TABLE_BT_REG,
    pub dport_ahblite_mpu_table_bt_buffer_reg: DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG,
    pub dport_ahblite_mpu_table_i2c_ext0_reg: DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG,
    pub dport_ahblite_mpu_table_uhci0_reg: DPORT_AHBLITE_MPU_TABLE_UHCI0_REG,
    pub dport_ahblite_mpu_table_slchost_reg: DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG,
    pub dport_ahblite_mpu_table_rmt_reg: DPORT_AHBLITE_MPU_TABLE_RMT_REG,
    pub dport_ahblite_mpu_table_pcnt_reg: DPORT_AHBLITE_MPU_TABLE_PCNT_REG,
    pub dport_ahblite_mpu_table_slc_reg: DPORT_AHBLITE_MPU_TABLE_SLC_REG,
    pub dport_ahblite_mpu_table_ledc_reg: DPORT_AHBLITE_MPU_TABLE_LEDC_REG,
    pub dport_ahblite_mpu_table_efuse_reg: DPORT_AHBLITE_MPU_TABLE_EFUSE_REG,
    pub dport_ahblite_mpu_table_spi_encrypt_reg: DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG,
    pub dport_ahblite_mpu_table_bb_reg: DPORT_AHBLITE_MPU_TABLE_BB_REG,
    pub dport_ahblite_mpu_table_pwm0_reg: DPORT_AHBLITE_MPU_TABLE_PWM0_REG,
    pub dport_ahblite_mpu_table_timergroup_reg: DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG,
    pub dport_ahblite_mpu_table_timergroup1_reg: DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG,
    pub dport_ahblite_mpu_table_spi2_reg: DPORT_AHBLITE_MPU_TABLE_SPI2_REG,
    pub dport_ahblite_mpu_table_spi3_reg: DPORT_AHBLITE_MPU_TABLE_SPI3_REG,
    pub dport_ahblite_mpu_table_apb_ctrl_reg: DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG,
    pub dport_ahblite_mpu_table_i2c_ext1_reg: DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG,
    pub dport_ahblite_mpu_table_sdio_host_reg: DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG,
    pub dport_ahblite_mpu_table_emac_reg: DPORT_AHBLITE_MPU_TABLE_EMAC_REG,
    pub dport_ahblite_mpu_table_can_reg: DPORT_AHBLITE_MPU_TABLE_CAN_REG,
    pub dport_ahblite_mpu_table_pwm1_reg: DPORT_AHBLITE_MPU_TABLE_PWM1_REG,
    pub dport_ahblite_mpu_table_i2s1_reg: DPORT_AHBLITE_MPU_TABLE_I2S1_REG,
    pub dport_ahblite_mpu_table_uart2_reg: DPORT_AHBLITE_MPU_TABLE_UART2_REG,
    pub dport_ahblite_mpu_table_pwm2_reg: DPORT_AHBLITE_MPU_TABLE_PWM2_REG,
    pub dport_ahblite_mpu_table_pwm3_reg: DPORT_AHBLITE_MPU_TABLE_PWM3_REG,
    pub dport_ahblite_mpu_table_rwbt_reg: DPORT_AHBLITE_MPU_TABLE_RWBT_REG,
    pub dport_ahblite_mpu_table_btmac_reg: DPORT_AHBLITE_MPU_TABLE_BTMAC_REG,
    pub dport_ahblite_mpu_table_wifimac_reg: DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG,
    pub dport_ahblite_mpu_table_pwr_reg: DPORT_AHBLITE_MPU_TABLE_PWR_REG,
    pub dport_mem_access_dbug0_reg: DPORT_MEM_ACCESS_DBUG0_REG,
    pub dport_mem_access_dbug1_reg: DPORT_MEM_ACCESS_DBUG1_REG,
    pub dport_pro_dcache_dbug0_reg: DPORT_PRO_DCACHE_DBUG0_REG,
    pub dport_pro_dcache_dbug1_reg: DPORT_PRO_DCACHE_DBUG1_REG,
    pub dport_pro_dcache_dbug2_reg: DPORT_PRO_DCACHE_DBUG2_REG,
    pub dport_pro_dcache_dbug3_reg: DPORT_PRO_DCACHE_DBUG3_REG,
    pub dport_pro_dcache_dbug4_reg: DPORT_PRO_DCACHE_DBUG4_REG,
    pub dport_pro_dcache_dbug5_reg: DPORT_PRO_DCACHE_DBUG5_REG,
    pub dport_pro_dcache_dbug6_reg: DPORT_PRO_DCACHE_DBUG6_REG,
    pub dport_pro_dcache_dbug7_reg: DPORT_PRO_DCACHE_DBUG7_REG,
    pub dport_pro_dcache_dbug8_reg: DPORT_PRO_DCACHE_DBUG8_REG,
    pub dport_pro_dcache_dbug9_reg: DPORT_PRO_DCACHE_DBUG9_REG,
    pub dport_app_dcache_dbug0_reg: DPORT_APP_DCACHE_DBUG0_REG,
    pub dport_app_dcache_dbug1_reg: DPORT_APP_DCACHE_DBUG1_REG,
    pub dport_app_dcache_dbug2_reg: DPORT_APP_DCACHE_DBUG2_REG,
    pub dport_app_dcache_dbug3_reg: DPORT_APP_DCACHE_DBUG3_REG,
    pub dport_app_dcache_dbug4_reg: DPORT_APP_DCACHE_DBUG4_REG,
    pub dport_app_dcache_dbug5_reg: DPORT_APP_DCACHE_DBUG5_REG,
    pub dport_app_dcache_dbug6_reg: DPORT_APP_DCACHE_DBUG6_REG,
    pub dport_app_dcache_dbug7_reg: DPORT_APP_DCACHE_DBUG7_REG,
    pub dport_app_dcache_dbug8_reg: DPORT_APP_DCACHE_DBUG8_REG,
    pub dport_app_dcache_dbug9_reg: DPORT_APP_DCACHE_DBUG9_REG,
    pub dport_pro_cpu_record_ctrl_reg: DPORT_PRO_CPU_RECORD_CTRL_REG,
    pub dport_pro_cpu_record_status_reg: DPORT_PRO_CPU_RECORD_STATUS_REG,
    pub dport_pro_cpu_record_pid_reg: DPORT_PRO_CPU_RECORD_PID_REG,
    pub dport_pro_cpu_record_pdebuginst_reg: DPORT_PRO_CPU_RECORD_PDEBUGINST_REG,
    pub dport_pro_cpu_record_pdebugstatus_reg: DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG,
    pub dport_pro_cpu_record_pdebugdata_reg: DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG,
    pub dport_pro_cpu_record_pdebugpc_reg: DPORT_PRO_CPU_RECORD_PDEBUGPC_REG,
    pub dport_pro_cpu_record_pdebugls0stat_reg: DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG,
    pub dport_pro_cpu_record_pdebugls0addr_reg: DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG,
    pub dport_pro_cpu_record_pdebugls0data_reg: DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG,
    pub dport_app_cpu_record_ctrl_reg: DPORT_APP_CPU_RECORD_CTRL_REG,
    pub dport_app_cpu_record_status_reg: DPORT_APP_CPU_RECORD_STATUS_REG,
    pub dport_app_cpu_record_pid_reg: DPORT_APP_CPU_RECORD_PID_REG,
    pub dport_app_cpu_record_pdebuginst_reg: DPORT_APP_CPU_RECORD_PDEBUGINST_REG,
    pub dport_app_cpu_record_pdebugstatus_reg: DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG,
    pub dport_app_cpu_record_pdebugdata_reg: DPORT_APP_CPU_RECORD_PDEBUGDATA_REG,
    pub dport_app_cpu_record_pdebugpc_reg: DPORT_APP_CPU_RECORD_PDEBUGPC_REG,
    pub dport_app_cpu_record_pdebugls0stat_reg: DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG,
    pub dport_app_cpu_record_pdebugls0addr_reg: DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG,
    pub dport_app_cpu_record_pdebugls0data_reg: DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG,
    pub dport_rsa_pd_ctrl_reg: DPORT_RSA_PD_CTRL_REG,
    pub dport_rom_mpu_table0_reg: DPORT_ROM_MPU_TABLE0_REG,
    pub dport_rom_mpu_table1_reg: DPORT_ROM_MPU_TABLE1_REG,
    pub dport_rom_mpu_table2_reg: DPORT_ROM_MPU_TABLE2_REG,
    pub dport_rom_mpu_table3_reg: DPORT_ROM_MPU_TABLE3_REG,
    pub dport_shrom_mpu_table0_reg: DPORT_SHROM_MPU_TABLE0_REG,
    pub dport_shrom_mpu_table1_reg: DPORT_SHROM_MPU_TABLE1_REG,
    pub dport_shrom_mpu_table2_reg: DPORT_SHROM_MPU_TABLE2_REG,
    pub dport_shrom_mpu_table3_reg: DPORT_SHROM_MPU_TABLE3_REG,
    pub dport_shrom_mpu_table4_reg: DPORT_SHROM_MPU_TABLE4_REG,
    pub dport_shrom_mpu_table5_reg: DPORT_SHROM_MPU_TABLE5_REG,
    pub dport_shrom_mpu_table6_reg: DPORT_SHROM_MPU_TABLE6_REG,
    pub dport_shrom_mpu_table7_reg: DPORT_SHROM_MPU_TABLE7_REG,
    pub dport_shrom_mpu_table8_reg: DPORT_SHROM_MPU_TABLE8_REG,
    pub dport_shrom_mpu_table9_reg: DPORT_SHROM_MPU_TABLE9_REG,
    pub dport_shrom_mpu_table10_reg: DPORT_SHROM_MPU_TABLE10_REG,
    pub dport_shrom_mpu_table11_reg: DPORT_SHROM_MPU_TABLE11_REG,
    pub dport_shrom_mpu_table12_reg: DPORT_SHROM_MPU_TABLE12_REG,
    pub dport_shrom_mpu_table13_reg: DPORT_SHROM_MPU_TABLE13_REG,
    pub dport_shrom_mpu_table14_reg: DPORT_SHROM_MPU_TABLE14_REG,
    pub dport_shrom_mpu_table15_reg: DPORT_SHROM_MPU_TABLE15_REG,
    pub dport_shrom_mpu_table16_reg: DPORT_SHROM_MPU_TABLE16_REG,
    pub dport_shrom_mpu_table17_reg: DPORT_SHROM_MPU_TABLE17_REG,
    pub dport_shrom_mpu_table18_reg: DPORT_SHROM_MPU_TABLE18_REG,
    pub dport_shrom_mpu_table19_reg: DPORT_SHROM_MPU_TABLE19_REG,
    pub dport_shrom_mpu_table20_reg: DPORT_SHROM_MPU_TABLE20_REG,
    pub dport_shrom_mpu_table21_reg: DPORT_SHROM_MPU_TABLE21_REG,
    pub dport_shrom_mpu_table22_reg: DPORT_SHROM_MPU_TABLE22_REG,
    pub dport_shrom_mpu_table23_reg: DPORT_SHROM_MPU_TABLE23_REG,
    pub dport_immu_table0_reg: DPORT_IMMU_TABLE0_REG,
    pub dport_immu_table1_reg: DPORT_IMMU_TABLE1_REG,
    pub dport_immu_table2_reg: DPORT_IMMU_TABLE2_REG,
    pub dport_immu_table3_reg: DPORT_IMMU_TABLE3_REG,
    pub dport_immu_table4_reg: DPORT_IMMU_TABLE4_REG,
    pub dport_immu_table5_reg: DPORT_IMMU_TABLE5_REG,
    pub dport_immu_table6_reg: DPORT_IMMU_TABLE6_REG,
    pub dport_immu_table7_reg: DPORT_IMMU_TABLE7_REG,
    pub dport_immu_table8_reg: DPORT_IMMU_TABLE8_REG,
    pub dport_immu_table9_reg: DPORT_IMMU_TABLE9_REG,
    pub dport_immu_table10_reg: DPORT_IMMU_TABLE10_REG,
    pub dport_immu_table11_reg: DPORT_IMMU_TABLE11_REG,
    pub dport_immu_table12_reg: DPORT_IMMU_TABLE12_REG,
    pub dport_immu_table13_reg: DPORT_IMMU_TABLE13_REG,
    pub dport_immu_table14_reg: DPORT_IMMU_TABLE14_REG,
    pub dport_immu_table15_reg: DPORT_IMMU_TABLE15_REG,
    pub dport_dmmu_table0_reg: DPORT_DMMU_TABLE0_REG,
    pub dport_dmmu_table1_reg: DPORT_DMMU_TABLE1_REG,
    pub dport_dmmu_table2_reg: DPORT_DMMU_TABLE2_REG,
    pub dport_dmmu_table3_reg: DPORT_DMMU_TABLE3_REG,
    pub dport_dmmu_table4_reg: DPORT_DMMU_TABLE4_REG,
    pub dport_dmmu_table5_reg: DPORT_DMMU_TABLE5_REG,
    pub dport_dmmu_table6_reg: DPORT_DMMU_TABLE6_REG,
    pub dport_dmmu_table7_reg: DPORT_DMMU_TABLE7_REG,
    pub dport_dmmu_table8_reg: DPORT_DMMU_TABLE8_REG,
    pub dport_dmmu_table9_reg: DPORT_DMMU_TABLE9_REG,
    pub dport_dmmu_table10_reg: DPORT_DMMU_TABLE10_REG,
    pub dport_dmmu_table11_reg: DPORT_DMMU_TABLE11_REG,
    pub dport_dmmu_table12_reg: DPORT_DMMU_TABLE12_REG,
    pub dport_dmmu_table13_reg: DPORT_DMMU_TABLE13_REG,
    pub dport_dmmu_table14_reg: DPORT_DMMU_TABLE14_REG,
    pub dport_dmmu_table15_reg: DPORT_DMMU_TABLE15_REG,
    pub dport_pro_intrusion_ctrl_reg: DPORT_PRO_INTRUSION_CTRL_REG,
    pub dport_pro_intrusion_status_reg: DPORT_PRO_INTRUSION_STATUS_REG,
    pub dport_app_intrusion_ctrl_reg: DPORT_APP_INTRUSION_CTRL_REG,
    pub dport_app_intrusion_status_reg: DPORT_APP_INTRUSION_STATUS_REG,
    pub dport_front_end_mem_pd_reg: DPORT_FRONT_END_MEM_PD_REG,
    pub dport_mmu_ia_int_en_reg: DPORT_MMU_IA_INT_EN_REG,
    pub dport_mpu_ia_int_en_reg: DPORT_MPU_IA_INT_EN_REG,
    pub dport_cache_ia_int_en_reg: DPORT_CACHE_IA_INT_EN_REG,
    pub dport_secure_boot_ctrl_reg: DPORT_SECURE_BOOT_CTRL_REG,
    pub dport_spi_dma_chan_sel_reg: DPORT_SPI_DMA_CHAN_SEL_REG,
    pub dport_pro_vecbase_ctrl_reg: DPORT_PRO_VECBASE_CTRL_REG,
    pub dport_pro_vecbase_set_reg: DPORT_PRO_VECBASE_SET_REG,
    pub dport_app_vecbase_ctrl_reg: DPORT_APP_VECBASE_CTRL_REG,
    pub dport_app_vecbase_set_reg: DPORT_APP_VECBASE_SET_REG,
    pub dport_date_reg: DPORT_DATE_REG,
    // some fields omitted
}

Register block

Fields

dport_pro_boot_remap_ctrl_reg: DPORT_PRO_BOOT_REMAP_CTRL_REG

0x00 - DPORT_PRO_BOOT_REMAP_CTRL_REG

dport_app_boot_remap_ctrl_reg: DPORT_APP_BOOT_REMAP_CTRL_REG

0x04 - DPORT_APP_BOOT_REMAP_CTRL_REG

dport_access_check_reg: DPORT_ACCESS_CHECK_REG

0x08 - DPORT_ACCESS_CHECK_REG

dport_pro_dport_apb_mask0_reg: DPORT_PRO_DPORT_APB_MASK0_REG

0x0c - DPORT_PRO_DPORT_APB_MASK0_REG

dport_pro_dport_apb_mask1_reg: DPORT_PRO_DPORT_APB_MASK1_REG

0x10 - DPORT_PRO_DPORT_APB_MASK1_REG

dport_app_dport_apb_mask0_reg: DPORT_APP_DPORT_APB_MASK0_REG

0x14 - DPORT_APP_DPORT_APB_MASK0_REG

dport_app_dport_apb_mask1_reg: DPORT_APP_DPORT_APB_MASK1_REG

0x18 - DPORT_APP_DPORT_APB_MASK1_REG

dport_peri_clk_en_reg: DPORT_PERI_CLK_EN_REG

0x1c - DPORT_PERI_CLK_EN_REG

dport_peri_rst_en_reg: DPORT_PERI_RST_EN_REG

0x20 - DPORT_PERI_RST_EN_REG

dport_wifi_bb_cfg_reg: DPORT_WIFI_BB_CFG_REG

0x24 - DPORT_WIFI_BB_CFG_REG

dport_wifi_bb_cfg_2_reg: DPORT_WIFI_BB_CFG_2_REG

0x28 - DPORT_WIFI_BB_CFG_2_REG

dport_appcpu_ctrl_a_reg: DPORT_APPCPU_CTRL_A_REG

0x2c - DPORT_APPCPU_CTRL_A_REG

dport_appcpu_ctrl_b_reg: DPORT_APPCPU_CTRL_B_REG

0x30 - DPORT_APPCPU_CTRL_B_REG

dport_appcpu_ctrl_c_reg: DPORT_APPCPU_CTRL_C_REG

0x34 - DPORT_APPCPU_CTRL_C_REG

dport_appcpu_ctrl_d_reg: DPORT_APPCPU_CTRL_D_REG

0x38 - DPORT_APPCPU_CTRL_D_REG

dport_cpu_per_conf_reg: DPORT_CPU_PER_CONF_REG

0x3c - DPORT_CPU_PER_CONF_REG

dport_pro_cache_ctrl_reg: DPORT_PRO_CACHE_CTRL_REG

0x40 - DPORT_PRO_CACHE_CTRL_REG

dport_pro_cache_ctrl1_reg: DPORT_PRO_CACHE_CTRL1_REG

0x44 - DPORT_PRO_CACHE_CTRL1_REG

dport_pro_cache_lock_0_addr_reg: DPORT_PRO_CACHE_LOCK_0_ADDR_REG

0x48 - DPORT_PRO_CACHE_LOCK_0_ADDR_REG

dport_pro_cache_lock_1_addr_reg: DPORT_PRO_CACHE_LOCK_1_ADDR_REG

0x4c - DPORT_PRO_CACHE_LOCK_1_ADDR_REG

dport_pro_cache_lock_2_addr_reg: DPORT_PRO_CACHE_LOCK_2_ADDR_REG

0x50 - DPORT_PRO_CACHE_LOCK_2_ADDR_REG

dport_pro_cache_lock_3_addr_reg: DPORT_PRO_CACHE_LOCK_3_ADDR_REG

0x54 - DPORT_PRO_CACHE_LOCK_3_ADDR_REG

dport_app_cache_ctrl_reg: DPORT_APP_CACHE_CTRL_REG

0x58 - DPORT_APP_CACHE_CTRL_REG

dport_app_cache_ctrl1_reg: DPORT_APP_CACHE_CTRL1_REG

0x5c - DPORT_APP_CACHE_CTRL1_REG

dport_app_cache_lock_0_addr_reg: DPORT_APP_CACHE_LOCK_0_ADDR_REG

0x60 - DPORT_APP_CACHE_LOCK_0_ADDR_REG

dport_app_cache_lock_1_addr_reg: DPORT_APP_CACHE_LOCK_1_ADDR_REG

0x64 - DPORT_APP_CACHE_LOCK_1_ADDR_REG

dport_app_cache_lock_2_addr_reg: DPORT_APP_CACHE_LOCK_2_ADDR_REG

0x68 - DPORT_APP_CACHE_LOCK_2_ADDR_REG

dport_app_cache_lock_3_addr_reg: DPORT_APP_CACHE_LOCK_3_ADDR_REG

0x6c - DPORT_APP_CACHE_LOCK_3_ADDR_REG

dport_tracemem_mux_mode_reg: DPORT_TRACEMEM_MUX_MODE_REG

0x70 - DPORT_TRACEMEM_MUX_MODE_REG

dport_pro_tracemem_ena_reg: DPORT_PRO_TRACEMEM_ENA_REG

0x74 - DPORT_PRO_TRACEMEM_ENA_REG

dport_app_tracemem_ena_reg: DPORT_APP_TRACEMEM_ENA_REG

0x78 - DPORT_APP_TRACEMEM_ENA_REG

dport_cache_mux_mode_reg: DPORT_CACHE_MUX_MODE_REG

0x7c - DPORT_CACHE_MUX_MODE_REG

dport_immu_page_mode_reg: DPORT_IMMU_PAGE_MODE_REG

0x80 - DPORT_IMMU_PAGE_MODE_REG

dport_dmmu_page_mode_reg: DPORT_DMMU_PAGE_MODE_REG

0x84 - DPORT_DMMU_PAGE_MODE_REG

dport_rom_mpu_ena_reg: DPORT_ROM_MPU_ENA_REG

0x88 - DPORT_ROM_MPU_ENA_REG

dport_mem_pd_mask_reg: DPORT_MEM_PD_MASK_REG

0x8c - DPORT_MEM_PD_MASK_REG

dport_rom_pd_ctrl_reg: DPORT_ROM_PD_CTRL_REG

0x90 - DPORT_ROM_PD_CTRL_REG

dport_rom_fo_ctrl_reg: DPORT_ROM_FO_CTRL_REG

0x94 - DPORT_ROM_FO_CTRL_REG

dport_sram_pd_ctrl_0_reg: DPORT_SRAM_PD_CTRL_0_REG

0x98 - DPORT_SRAM_PD_CTRL_0_REG

dport_sram_pd_ctrl_1_reg: DPORT_SRAM_PD_CTRL_1_REG

0x9c - DPORT_SRAM_PD_CTRL_1_REG

dport_sram_fo_ctrl_0_reg: DPORT_SRAM_FO_CTRL_0_REG

0xa0 - DPORT_SRAM_FO_CTRL_0_REG

dport_sram_fo_ctrl_1_reg: DPORT_SRAM_FO_CTRL_1_REG

0xa4 - DPORT_SRAM_FO_CTRL_1_REG

dport_iram_dram_ahb_sel_reg: DPORT_IRAM_DRAM_AHB_SEL_REG

0xa8 - DPORT_IRAM_DRAM_AHB_SEL_REG

dport_tag_fo_ctrl_reg: DPORT_TAG_FO_CTRL_REG

0xac - DPORT_TAG_FO_CTRL_REG

dport_ahb_lite_mask_reg: DPORT_AHB_LITE_MASK_REG

0xb0 - DPORT_AHB_LITE_MASK_REG

dport_ahb_mpu_table_0_reg: DPORT_AHB_MPU_TABLE_0_REG

0xb4 - DPORT_AHB_MPU_TABLE_0_REG

dport_ahb_mpu_table_1_reg: DPORT_AHB_MPU_TABLE_1_REG

0xb8 - DPORT_AHB_MPU_TABLE_1_REG

dport_host_inf_sel_reg: DPORT_HOST_INF_SEL_REG

0xbc - DPORT_HOST_INF_SEL_REG

dport_perip_clk_en_reg: DPORT_PERIP_CLK_EN_REG

0xc0 - DPORT_PERIP_CLK_EN_REG

dport_perip_rst_en_reg: DPORT_PERIP_RST_EN_REG

0xc4 - DPORT_PERIP_RST_EN_REG

dport_wifi_clk_en_reg: DPORT_WIFI_CLK_EN_REG

0xcc - DPORT_WIFI_CLK_EN_REG

dport_core_rst_en_reg: DPORT_CORE_RST_EN_REG

0xd0 - DPORT_CORE_RST_EN_REG

dport_bt_lpck_div_int_reg: DPORT_BT_LPCK_DIV_INT_REG

0xd4 - DPORT_BT_LPCK_DIV_INT_REG

dport_bt_lpck_div_frac_reg: DPORT_BT_LPCK_DIV_FRAC_REG

0xd8 - DPORT_BT_LPCK_DIV_FRAC_REG

dport_cpu_intr_from_cpu_0_reg: DPORT_CPU_INTR_FROM_CPU_0_REG

0xdc - DPORT_CPU_INTR_FROM_CPU_0_REG

dport_cpu_intr_from_cpu_1_reg: DPORT_CPU_INTR_FROM_CPU_1_REG

0xe0 - DPORT_CPU_INTR_FROM_CPU_1_REG

dport_cpu_intr_from_cpu_2_reg: DPORT_CPU_INTR_FROM_CPU_2_REG

0xe4 - DPORT_CPU_INTR_FROM_CPU_2_REG

dport_cpu_intr_from_cpu_3_reg: DPORT_CPU_INTR_FROM_CPU_3_REG

0xe8 - DPORT_CPU_INTR_FROM_CPU_3_REG

dport_pro_intr_status_0_reg: DPORT_PRO_INTR_STATUS_0_REG

0xec - DPORT_PRO_INTR_STATUS_0_REG

dport_pro_intr_status_1_reg: DPORT_PRO_INTR_STATUS_1_REG

0xf0 - DPORT_PRO_INTR_STATUS_1_REG

dport_pro_intr_status_2_reg: DPORT_PRO_INTR_STATUS_2_REG

0xf4 - DPORT_PRO_INTR_STATUS_2_REG

dport_app_intr_status_0_reg: DPORT_APP_INTR_STATUS_0_REG

0xf8 - DPORT_APP_INTR_STATUS_0_REG

dport_app_intr_status_1_reg: DPORT_APP_INTR_STATUS_1_REG

0xfc - DPORT_APP_INTR_STATUS_1_REG

dport_app_intr_status_2_reg: DPORT_APP_INTR_STATUS_2_REG

0x100 - DPORT_APP_INTR_STATUS_2_REG

dport_pro_mac_intr_map_reg: DPORT_PRO_MAC_INTR_MAP_REG

0x104 - DPORT_PRO_MAC_INTR_MAP_REG

dport_pro_mac_nmi_map_reg: DPORT_PRO_MAC_NMI_MAP_REG

0x108 - DPORT_PRO_MAC_NMI_MAP_REG

dport_pro_bb_int_map_reg: DPORT_PRO_BB_INT_MAP_REG

0x10c - DPORT_PRO_BB_INT_MAP_REG

dport_pro_bt_mac_int_map_reg: DPORT_PRO_BT_MAC_INT_MAP_REG

0x110 - DPORT_PRO_BT_MAC_INT_MAP_REG

dport_pro_bt_bb_int_map_reg: DPORT_PRO_BT_BB_INT_MAP_REG

0x114 - DPORT_PRO_BT_BB_INT_MAP_REG

dport_pro_bt_bb_nmi_map_reg: DPORT_PRO_BT_BB_NMI_MAP_REG

0x118 - DPORT_PRO_BT_BB_NMI_MAP_REG

dport_pro_rwbt_irq_map_reg: DPORT_PRO_RWBT_IRQ_MAP_REG

0x11c - DPORT_PRO_RWBT_IRQ_MAP_REG

dport_pro_rwble_irq_map_reg: DPORT_PRO_RWBLE_IRQ_MAP_REG

0x120 - DPORT_PRO_RWBLE_IRQ_MAP_REG

dport_pro_rwbt_nmi_map_reg: DPORT_PRO_RWBT_NMI_MAP_REG

0x124 - DPORT_PRO_RWBT_NMI_MAP_REG

dport_pro_rwble_nmi_map_reg: DPORT_PRO_RWBLE_NMI_MAP_REG

0x128 - DPORT_PRO_RWBLE_NMI_MAP_REG

dport_pro_slc0_intr_map_reg: DPORT_PRO_SLC0_INTR_MAP_REG

0x12c - DPORT_PRO_SLC0_INTR_MAP_REG

dport_pro_slc1_intr_map_reg: DPORT_PRO_SLC1_INTR_MAP_REG

0x130 - DPORT_PRO_SLC1_INTR_MAP_REG

dport_pro_uhci0_intr_map_reg: DPORT_PRO_UHCI0_INTR_MAP_REG

0x134 - DPORT_PRO_UHCI0_INTR_MAP_REG

dport_pro_uhci1_intr_map_reg: DPORT_PRO_UHCI1_INTR_MAP_REG

0x138 - DPORT_PRO_UHCI1_INTR_MAP_REG

dport_pro_tg_t0_level_int_map_reg: DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG

0x13c - DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG

dport_pro_tg_t1_level_int_map_reg: DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG

0x140 - DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG

dport_pro_tg_wdt_level_int_map_reg: DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG

0x144 - DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG

dport_pro_tg_lact_level_int_map_reg: DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG

0x148 - DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG

dport_pro_tg1_t0_level_int_map_reg: DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG

0x14c - DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG

dport_pro_tg1_t1_level_int_map_reg: DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG

0x150 - DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG

dport_pro_tg1_wdt_level_int_map_reg: DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG

0x154 - DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG

dport_pro_tg1_lact_level_int_map_reg: DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG

0x158 - DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG

dport_pro_gpio_interrupt_map_reg: DPORT_PRO_GPIO_INTERRUPT_MAP_REG

0x15c - DPORT_PRO_GPIO_INTERRUPT_MAP_REG

dport_pro_gpio_interrupt_nmi_map_reg: DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG

0x160 - DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG

dport_pro_cpu_intr_from_cpu_0_map_reg: DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG

0x164 - DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG

dport_pro_cpu_intr_from_cpu_1_map_reg: DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG

0x168 - DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG

dport_pro_cpu_intr_from_cpu_2_map_reg: DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG

0x16c - DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG

dport_pro_cpu_intr_from_cpu_3_map_reg: DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG

0x170 - DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG

dport_pro_spi_intr_0_map_reg: DPORT_PRO_SPI_INTR_0_MAP_REG

0x174 - DPORT_PRO_SPI_INTR_0_MAP_REG

dport_pro_spi_intr_1_map_reg: DPORT_PRO_SPI_INTR_1_MAP_REG

0x178 - DPORT_PRO_SPI_INTR_1_MAP_REG

dport_pro_spi_intr_2_map_reg: DPORT_PRO_SPI_INTR_2_MAP_REG

0x17c - DPORT_PRO_SPI_INTR_2_MAP_REG

dport_pro_spi_intr_3_map_reg: DPORT_PRO_SPI_INTR_3_MAP_REG

0x180 - DPORT_PRO_SPI_INTR_3_MAP_REG

dport_pro_i2s0_int_map_reg: DPORT_PRO_I2S0_INT_MAP_REG

0x184 - DPORT_PRO_I2S0_INT_MAP_REG

dport_pro_i2s1_int_map_reg: DPORT_PRO_I2S1_INT_MAP_REG

0x188 - DPORT_PRO_I2S1_INT_MAP_REG

dport_pro_uart_intr_map_reg: DPORT_PRO_UART_INTR_MAP_REG

0x18c - DPORT_PRO_UART_INTR_MAP_REG

dport_pro_uart1_intr_map_reg: DPORT_PRO_UART1_INTR_MAP_REG

0x190 - DPORT_PRO_UART1_INTR_MAP_REG

dport_pro_uart2_intr_map_reg: DPORT_PRO_UART2_INTR_MAP_REG

0x194 - DPORT_PRO_UART2_INTR_MAP_REG

dport_pro_sdio_host_interrupt_map_reg: DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG

0x198 - DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG

dport_pro_emac_int_map_reg: DPORT_PRO_EMAC_INT_MAP_REG

0x19c - DPORT_PRO_EMAC_INT_MAP_REG

dport_pro_pwm0_intr_map_reg: DPORT_PRO_PWM0_INTR_MAP_REG

0x1a0 - DPORT_PRO_PWM0_INTR_MAP_REG

dport_pro_pwm1_intr_map_reg: DPORT_PRO_PWM1_INTR_MAP_REG

0x1a4 - DPORT_PRO_PWM1_INTR_MAP_REG

dport_pro_pwm2_intr_map_reg: DPORT_PRO_PWM2_INTR_MAP_REG

0x1a8 - DPORT_PRO_PWM2_INTR_MAP_REG

dport_pro_pwm3_intr_map_reg: DPORT_PRO_PWM3_INTR_MAP_REG

0x1ac - DPORT_PRO_PWM3_INTR_MAP_REG

dport_pro_ledc_int_map_reg: DPORT_PRO_LEDC_INT_MAP_REG

0x1b0 - DPORT_PRO_LEDC_INT_MAP_REG

dport_pro_efuse_int_map_reg: DPORT_PRO_EFUSE_INT_MAP_REG

0x1b4 - DPORT_PRO_EFUSE_INT_MAP_REG

dport_pro_can_int_map_reg: DPORT_PRO_CAN_INT_MAP_REG

0x1b8 - DPORT_PRO_CAN_INT_MAP_REG

dport_pro_rtc_core_intr_map_reg: DPORT_PRO_RTC_CORE_INTR_MAP_REG

0x1bc - DPORT_PRO_RTC_CORE_INTR_MAP_REG

dport_pro_rmt_intr_map_reg: DPORT_PRO_RMT_INTR_MAP_REG

0x1c0 - DPORT_PRO_RMT_INTR_MAP_REG

dport_pro_pcnt_intr_map_reg: DPORT_PRO_PCNT_INTR_MAP_REG

0x1c4 - DPORT_PRO_PCNT_INTR_MAP_REG

dport_pro_i2c_ext0_intr_map_reg: DPORT_PRO_I2C_EXT0_INTR_MAP_REG

0x1c8 - DPORT_PRO_I2C_EXT0_INTR_MAP_REG

dport_pro_i2c_ext1_intr_map_reg: DPORT_PRO_I2C_EXT1_INTR_MAP_REG

0x1cc - DPORT_PRO_I2C_EXT1_INTR_MAP_REG

dport_pro_rsa_intr_map_reg: DPORT_PRO_RSA_INTR_MAP_REG

0x1d0 - DPORT_PRO_RSA_INTR_MAP_REG

dport_pro_spi1_dma_int_map_reg: DPORT_PRO_SPI1_DMA_INT_MAP_REG

0x1d4 - DPORT_PRO_SPI1_DMA_INT_MAP_REG

dport_pro_spi2_dma_int_map_reg: DPORT_PRO_SPI2_DMA_INT_MAP_REG

0x1d8 - DPORT_PRO_SPI2_DMA_INT_MAP_REG

dport_pro_spi3_dma_int_map_reg: DPORT_PRO_SPI3_DMA_INT_MAP_REG

0x1dc - DPORT_PRO_SPI3_DMA_INT_MAP_REG

dport_pro_wdg_int_map_reg: DPORT_PRO_WDG_INT_MAP_REG

0x1e0 - DPORT_PRO_WDG_INT_MAP_REG

dport_pro_timer_int1_map_reg: DPORT_PRO_TIMER_INT1_MAP_REG

0x1e4 - DPORT_PRO_TIMER_INT1_MAP_REG

dport_pro_timer_int2_map_reg: DPORT_PRO_TIMER_INT2_MAP_REG

0x1e8 - DPORT_PRO_TIMER_INT2_MAP_REG

dport_pro_tg_t0_edge_int_map_reg: DPORT_PRO_TG_T0_EDGE_INT_MAP_REG

0x1ec - DPORT_PRO_TG_T0_EDGE_INT_MAP_REG

dport_pro_tg_t1_edge_int_map_reg: DPORT_PRO_TG_T1_EDGE_INT_MAP_REG

0x1f0 - DPORT_PRO_TG_T1_EDGE_INT_MAP_REG

dport_pro_tg_wdt_edge_int_map_reg: DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG

0x1f4 - DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG

dport_pro_tg_lact_edge_int_map_reg: DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG

0x1f8 - DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG

dport_pro_tg1_t0_edge_int_map_reg: DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG

0x1fc - DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG

dport_pro_tg1_t1_edge_int_map_reg: DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG

0x200 - DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG

dport_pro_tg1_wdt_edge_int_map_reg: DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG

0x204 - DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG

dport_pro_tg1_lact_edge_int_map_reg: DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG

0x208 - DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG

dport_pro_mmu_ia_int_map_reg: DPORT_PRO_MMU_IA_INT_MAP_REG

0x20c - DPORT_PRO_MMU_IA_INT_MAP_REG

dport_pro_mpu_ia_int_map_reg: DPORT_PRO_MPU_IA_INT_MAP_REG

0x210 - DPORT_PRO_MPU_IA_INT_MAP_REG

dport_pro_cache_ia_int_map_reg: DPORT_PRO_CACHE_IA_INT_MAP_REG

0x214 - DPORT_PRO_CACHE_IA_INT_MAP_REG

dport_app_mac_intr_map_reg: DPORT_APP_MAC_INTR_MAP_REG

0x218 - DPORT_APP_MAC_INTR_MAP_REG

dport_app_mac_nmi_map_reg: DPORT_APP_MAC_NMI_MAP_REG

0x21c - DPORT_APP_MAC_NMI_MAP_REG

dport_app_bb_int_map_reg: DPORT_APP_BB_INT_MAP_REG

0x220 - DPORT_APP_BB_INT_MAP_REG

dport_app_bt_mac_int_map_reg: DPORT_APP_BT_MAC_INT_MAP_REG

0x224 - DPORT_APP_BT_MAC_INT_MAP_REG

dport_app_bt_bb_int_map_reg: DPORT_APP_BT_BB_INT_MAP_REG

0x228 - DPORT_APP_BT_BB_INT_MAP_REG

dport_app_bt_bb_nmi_map_reg: DPORT_APP_BT_BB_NMI_MAP_REG

0x22c - DPORT_APP_BT_BB_NMI_MAP_REG

dport_app_rwbt_irq_map_reg: DPORT_APP_RWBT_IRQ_MAP_REG

0x230 - DPORT_APP_RWBT_IRQ_MAP_REG

dport_app_rwble_irq_map_reg: DPORT_APP_RWBLE_IRQ_MAP_REG

0x234 - DPORT_APP_RWBLE_IRQ_MAP_REG

dport_app_rwbt_nmi_map_reg: DPORT_APP_RWBT_NMI_MAP_REG

0x238 - DPORT_APP_RWBT_NMI_MAP_REG

dport_app_rwble_nmi_map_reg: DPORT_APP_RWBLE_NMI_MAP_REG

0x23c - DPORT_APP_RWBLE_NMI_MAP_REG

dport_app_slc0_intr_map_reg: DPORT_APP_SLC0_INTR_MAP_REG

0x240 - DPORT_APP_SLC0_INTR_MAP_REG

dport_app_slc1_intr_map_reg: DPORT_APP_SLC1_INTR_MAP_REG

0x244 - DPORT_APP_SLC1_INTR_MAP_REG

dport_app_uhci0_intr_map_reg: DPORT_APP_UHCI0_INTR_MAP_REG

0x248 - DPORT_APP_UHCI0_INTR_MAP_REG

dport_app_uhci1_intr_map_reg: DPORT_APP_UHCI1_INTR_MAP_REG

0x24c - DPORT_APP_UHCI1_INTR_MAP_REG

dport_app_tg_t0_level_int_map_reg: DPORT_APP_TG_T0_LEVEL_INT_MAP_REG

0x250 - DPORT_APP_TG_T0_LEVEL_INT_MAP_REG

dport_app_tg_t1_level_int_map_reg: DPORT_APP_TG_T1_LEVEL_INT_MAP_REG

0x254 - DPORT_APP_TG_T1_LEVEL_INT_MAP_REG

dport_app_tg_wdt_level_int_map_reg: DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG

0x258 - DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG

dport_app_tg_lact_level_int_map_reg: DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG

0x25c - DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG

dport_app_tg1_t0_level_int_map_reg: DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG

0x260 - DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG

dport_app_tg1_t1_level_int_map_reg: DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG

0x264 - DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG

dport_app_tg1_wdt_level_int_map_reg: DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG

0x268 - DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG

dport_app_tg1_lact_level_int_map_reg: DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG

0x26c - DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG

dport_app_gpio_interrupt_map_reg: DPORT_APP_GPIO_INTERRUPT_MAP_REG

0x270 - DPORT_APP_GPIO_INTERRUPT_MAP_REG

dport_app_gpio_interrupt_nmi_map_reg: DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG

0x274 - DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG

dport_app_cpu_intr_from_cpu_0_map_reg: DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG

0x278 - DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG

dport_app_cpu_intr_from_cpu_1_map_reg: DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG

0x27c - DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG

dport_app_cpu_intr_from_cpu_2_map_reg: DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG

0x280 - DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG

dport_app_cpu_intr_from_cpu_3_map_reg: DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG

0x284 - DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG

dport_app_spi_intr_0_map_reg: DPORT_APP_SPI_INTR_0_MAP_REG

0x288 - DPORT_APP_SPI_INTR_0_MAP_REG

dport_app_spi_intr_1_map_reg: DPORT_APP_SPI_INTR_1_MAP_REG

0x28c - DPORT_APP_SPI_INTR_1_MAP_REG

dport_app_spi_intr_2_map_reg: DPORT_APP_SPI_INTR_2_MAP_REG

0x290 - DPORT_APP_SPI_INTR_2_MAP_REG

dport_app_spi_intr_3_map_reg: DPORT_APP_SPI_INTR_3_MAP_REG

0x294 - DPORT_APP_SPI_INTR_3_MAP_REG

dport_app_i2s0_int_map_reg: DPORT_APP_I2S0_INT_MAP_REG

0x298 - DPORT_APP_I2S0_INT_MAP_REG

dport_app_i2s1_int_map_reg: DPORT_APP_I2S1_INT_MAP_REG

0x29c - DPORT_APP_I2S1_INT_MAP_REG

dport_app_uart_intr_map_reg: DPORT_APP_UART_INTR_MAP_REG

0x2a0 - DPORT_APP_UART_INTR_MAP_REG

dport_app_uart1_intr_map_reg: DPORT_APP_UART1_INTR_MAP_REG

0x2a4 - DPORT_APP_UART1_INTR_MAP_REG

dport_app_uart2_intr_map_reg: DPORT_APP_UART2_INTR_MAP_REG

0x2a8 - DPORT_APP_UART2_INTR_MAP_REG

dport_app_sdio_host_interrupt_map_reg: DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG

0x2ac - DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG

dport_app_emac_int_map_reg: DPORT_APP_EMAC_INT_MAP_REG

0x2b0 - DPORT_APP_EMAC_INT_MAP_REG

dport_app_pwm0_intr_map_reg: DPORT_APP_PWM0_INTR_MAP_REG

0x2b4 - DPORT_APP_PWM0_INTR_MAP_REG

dport_app_pwm1_intr_map_reg: DPORT_APP_PWM1_INTR_MAP_REG

0x2b8 - DPORT_APP_PWM1_INTR_MAP_REG

dport_app_pwm2_intr_map_reg: DPORT_APP_PWM2_INTR_MAP_REG

0x2bc - DPORT_APP_PWM2_INTR_MAP_REG

dport_app_pwm3_intr_map_reg: DPORT_APP_PWM3_INTR_MAP_REG

0x2c0 - DPORT_APP_PWM3_INTR_MAP_REG

dport_app_ledc_int_map_reg: DPORT_APP_LEDC_INT_MAP_REG

0x2c4 - DPORT_APP_LEDC_INT_MAP_REG

dport_app_efuse_int_map_reg: DPORT_APP_EFUSE_INT_MAP_REG

0x2c8 - DPORT_APP_EFUSE_INT_MAP_REG

dport_app_can_int_map_reg: DPORT_APP_CAN_INT_MAP_REG

0x2cc - DPORT_APP_CAN_INT_MAP_REG

dport_app_rtc_core_intr_map_reg: DPORT_APP_RTC_CORE_INTR_MAP_REG

0x2d0 - DPORT_APP_RTC_CORE_INTR_MAP_REG

dport_app_rmt_intr_map_reg: DPORT_APP_RMT_INTR_MAP_REG

0x2d4 - DPORT_APP_RMT_INTR_MAP_REG

dport_app_pcnt_intr_map_reg: DPORT_APP_PCNT_INTR_MAP_REG

0x2d8 - DPORT_APP_PCNT_INTR_MAP_REG

dport_app_i2c_ext0_intr_map_reg: DPORT_APP_I2C_EXT0_INTR_MAP_REG

0x2dc - DPORT_APP_I2C_EXT0_INTR_MAP_REG

dport_app_i2c_ext1_intr_map_reg: DPORT_APP_I2C_EXT1_INTR_MAP_REG

0x2e0 - DPORT_APP_I2C_EXT1_INTR_MAP_REG

dport_app_rsa_intr_map_reg: DPORT_APP_RSA_INTR_MAP_REG

0x2e4 - DPORT_APP_RSA_INTR_MAP_REG

dport_app_spi1_dma_int_map_reg: DPORT_APP_SPI1_DMA_INT_MAP_REG

0x2e8 - DPORT_APP_SPI1_DMA_INT_MAP_REG

dport_app_spi2_dma_int_map_reg: DPORT_APP_SPI2_DMA_INT_MAP_REG

0x2ec - DPORT_APP_SPI2_DMA_INT_MAP_REG

dport_app_spi3_dma_int_map_reg: DPORT_APP_SPI3_DMA_INT_MAP_REG

0x2f0 - DPORT_APP_SPI3_DMA_INT_MAP_REG

dport_app_wdg_int_map_reg: DPORT_APP_WDG_INT_MAP_REG

0x2f4 - DPORT_APP_WDG_INT_MAP_REG

dport_app_timer_int1_map_reg: DPORT_APP_TIMER_INT1_MAP_REG

0x2f8 - DPORT_APP_TIMER_INT1_MAP_REG

dport_app_timer_int2_map_reg: DPORT_APP_TIMER_INT2_MAP_REG

0x2fc - DPORT_APP_TIMER_INT2_MAP_REG

dport_app_tg_t0_edge_int_map_reg: DPORT_APP_TG_T0_EDGE_INT_MAP_REG

0x300 - DPORT_APP_TG_T0_EDGE_INT_MAP_REG

dport_app_tg_t1_edge_int_map_reg: DPORT_APP_TG_T1_EDGE_INT_MAP_REG

0x304 - DPORT_APP_TG_T1_EDGE_INT_MAP_REG

dport_app_tg_wdt_edge_int_map_reg: DPORT_APP_TG_WDT_EDGE_INT_MAP_REG

0x308 - DPORT_APP_TG_WDT_EDGE_INT_MAP_REG

dport_app_tg_lact_edge_int_map_reg: DPORT_APP_TG_LACT_EDGE_INT_MAP_REG

0x30c - DPORT_APP_TG_LACT_EDGE_INT_MAP_REG

dport_app_tg1_t0_edge_int_map_reg: DPORT_APP_TG1_T0_EDGE_INT_MAP_REG

0x310 - DPORT_APP_TG1_T0_EDGE_INT_MAP_REG

dport_app_tg1_t1_edge_int_map_reg: DPORT_APP_TG1_T1_EDGE_INT_MAP_REG

0x314 - DPORT_APP_TG1_T1_EDGE_INT_MAP_REG

dport_app_tg1_wdt_edge_int_map_reg: DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG

0x318 - DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG

dport_app_tg1_lact_edge_int_map_reg: DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG

0x31c - DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG

dport_app_mmu_ia_int_map_reg: DPORT_APP_MMU_IA_INT_MAP_REG

0x320 - DPORT_APP_MMU_IA_INT_MAP_REG

dport_app_mpu_ia_int_map_reg: DPORT_APP_MPU_IA_INT_MAP_REG

0x324 - DPORT_APP_MPU_IA_INT_MAP_REG

dport_app_cache_ia_int_map_reg: DPORT_APP_CACHE_IA_INT_MAP_REG

0x328 - DPORT_APP_CACHE_IA_INT_MAP_REG

dport_ahblite_mpu_table_uart_reg: DPORT_AHBLITE_MPU_TABLE_UART_REG

0x32c - DPORT_AHBLITE_MPU_TABLE_UART_REG

dport_ahblite_mpu_table_spi1_reg: DPORT_AHBLITE_MPU_TABLE_SPI1_REG

0x330 - DPORT_AHBLITE_MPU_TABLE_SPI1_REG

dport_ahblite_mpu_table_spi0_reg: DPORT_AHBLITE_MPU_TABLE_SPI0_REG

0x334 - DPORT_AHBLITE_MPU_TABLE_SPI0_REG

dport_ahblite_mpu_table_gpio_reg: DPORT_AHBLITE_MPU_TABLE_GPIO_REG

0x338 - DPORT_AHBLITE_MPU_TABLE_GPIO_REG

dport_ahblite_mpu_table_fe2_reg: DPORT_AHBLITE_MPU_TABLE_FE2_REG

0x33c - DPORT_AHBLITE_MPU_TABLE_FE2_REG

dport_ahblite_mpu_table_fe_reg: DPORT_AHBLITE_MPU_TABLE_FE_REG

0x340 - DPORT_AHBLITE_MPU_TABLE_FE_REG

dport_ahblite_mpu_table_timer_reg: DPORT_AHBLITE_MPU_TABLE_TIMER_REG

0x344 - DPORT_AHBLITE_MPU_TABLE_TIMER_REG

dport_ahblite_mpu_table_rtc_reg: DPORT_AHBLITE_MPU_TABLE_RTC_REG

0x348 - DPORT_AHBLITE_MPU_TABLE_RTC_REG

dport_ahblite_mpu_table_io_mux_reg: DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG

0x34c - DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG

dport_ahblite_mpu_table_wdg_reg: DPORT_AHBLITE_MPU_TABLE_WDG_REG

0x350 - DPORT_AHBLITE_MPU_TABLE_WDG_REG

dport_ahblite_mpu_table_hinf_reg: DPORT_AHBLITE_MPU_TABLE_HINF_REG

0x354 - DPORT_AHBLITE_MPU_TABLE_HINF_REG

dport_ahblite_mpu_table_uhci1_reg: DPORT_AHBLITE_MPU_TABLE_UHCI1_REG

0x358 - DPORT_AHBLITE_MPU_TABLE_UHCI1_REG

dport_ahblite_mpu_table_misc_reg: DPORT_AHBLITE_MPU_TABLE_MISC_REG

0x35c - DPORT_AHBLITE_MPU_TABLE_MISC_REG

dport_ahblite_mpu_table_i2c_reg: DPORT_AHBLITE_MPU_TABLE_I2C_REG

0x360 - DPORT_AHBLITE_MPU_TABLE_I2C_REG

dport_ahblite_mpu_table_i2s0_reg: DPORT_AHBLITE_MPU_TABLE_I2S0_REG

0x364 - DPORT_AHBLITE_MPU_TABLE_I2S0_REG

dport_ahblite_mpu_table_uart1_reg: DPORT_AHBLITE_MPU_TABLE_UART1_REG

0x368 - DPORT_AHBLITE_MPU_TABLE_UART1_REG

dport_ahblite_mpu_table_bt_reg: DPORT_AHBLITE_MPU_TABLE_BT_REG

0x36c - DPORT_AHBLITE_MPU_TABLE_BT_REG

dport_ahblite_mpu_table_bt_buffer_reg: DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG

0x370 - DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG

dport_ahblite_mpu_table_i2c_ext0_reg: DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG

0x374 - DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG

dport_ahblite_mpu_table_uhci0_reg: DPORT_AHBLITE_MPU_TABLE_UHCI0_REG

0x378 - DPORT_AHBLITE_MPU_TABLE_UHCI0_REG

dport_ahblite_mpu_table_slchost_reg: DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG

0x37c - DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG

dport_ahblite_mpu_table_rmt_reg: DPORT_AHBLITE_MPU_TABLE_RMT_REG

0x380 - DPORT_AHBLITE_MPU_TABLE_RMT_REG

dport_ahblite_mpu_table_pcnt_reg: DPORT_AHBLITE_MPU_TABLE_PCNT_REG

0x384 - DPORT_AHBLITE_MPU_TABLE_PCNT_REG

dport_ahblite_mpu_table_slc_reg: DPORT_AHBLITE_MPU_TABLE_SLC_REG

0x388 - DPORT_AHBLITE_MPU_TABLE_SLC_REG

dport_ahblite_mpu_table_ledc_reg: DPORT_AHBLITE_MPU_TABLE_LEDC_REG

0x38c - DPORT_AHBLITE_MPU_TABLE_LEDC_REG

dport_ahblite_mpu_table_efuse_reg: DPORT_AHBLITE_MPU_TABLE_EFUSE_REG

0x390 - DPORT_AHBLITE_MPU_TABLE_EFUSE_REG

dport_ahblite_mpu_table_spi_encrypt_reg: DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG

0x394 - DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG

dport_ahblite_mpu_table_bb_reg: DPORT_AHBLITE_MPU_TABLE_BB_REG

0x398 - DPORT_AHBLITE_MPU_TABLE_BB_REG

dport_ahblite_mpu_table_pwm0_reg: DPORT_AHBLITE_MPU_TABLE_PWM0_REG

0x39c - DPORT_AHBLITE_MPU_TABLE_PWM0_REG

dport_ahblite_mpu_table_timergroup_reg: DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG

0x3a0 - DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG

dport_ahblite_mpu_table_timergroup1_reg: DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG

0x3a4 - DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG

dport_ahblite_mpu_table_spi2_reg: DPORT_AHBLITE_MPU_TABLE_SPI2_REG

0x3a8 - DPORT_AHBLITE_MPU_TABLE_SPI2_REG

dport_ahblite_mpu_table_spi3_reg: DPORT_AHBLITE_MPU_TABLE_SPI3_REG

0x3ac - DPORT_AHBLITE_MPU_TABLE_SPI3_REG

dport_ahblite_mpu_table_apb_ctrl_reg: DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG

0x3b0 - DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG

dport_ahblite_mpu_table_i2c_ext1_reg: DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG

0x3b4 - DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG

dport_ahblite_mpu_table_sdio_host_reg: DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG

0x3b8 - DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG

dport_ahblite_mpu_table_emac_reg: DPORT_AHBLITE_MPU_TABLE_EMAC_REG

0x3bc - DPORT_AHBLITE_MPU_TABLE_EMAC_REG

dport_ahblite_mpu_table_can_reg: DPORT_AHBLITE_MPU_TABLE_CAN_REG

0x3c0 - DPORT_AHBLITE_MPU_TABLE_CAN_REG

dport_ahblite_mpu_table_pwm1_reg: DPORT_AHBLITE_MPU_TABLE_PWM1_REG

0x3c4 - DPORT_AHBLITE_MPU_TABLE_PWM1_REG

dport_ahblite_mpu_table_i2s1_reg: DPORT_AHBLITE_MPU_TABLE_I2S1_REG

0x3c8 - DPORT_AHBLITE_MPU_TABLE_I2S1_REG

dport_ahblite_mpu_table_uart2_reg: DPORT_AHBLITE_MPU_TABLE_UART2_REG

0x3cc - DPORT_AHBLITE_MPU_TABLE_UART2_REG

dport_ahblite_mpu_table_pwm2_reg: DPORT_AHBLITE_MPU_TABLE_PWM2_REG

0x3d0 - DPORT_AHBLITE_MPU_TABLE_PWM2_REG

dport_ahblite_mpu_table_pwm3_reg: DPORT_AHBLITE_MPU_TABLE_PWM3_REG

0x3d4 - DPORT_AHBLITE_MPU_TABLE_PWM3_REG

dport_ahblite_mpu_table_rwbt_reg: DPORT_AHBLITE_MPU_TABLE_RWBT_REG

0x3d8 - DPORT_AHBLITE_MPU_TABLE_RWBT_REG

dport_ahblite_mpu_table_btmac_reg: DPORT_AHBLITE_MPU_TABLE_BTMAC_REG

0x3dc - DPORT_AHBLITE_MPU_TABLE_BTMAC_REG

dport_ahblite_mpu_table_wifimac_reg: DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG

0x3e0 - DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG

dport_ahblite_mpu_table_pwr_reg: DPORT_AHBLITE_MPU_TABLE_PWR_REG

0x3e4 - DPORT_AHBLITE_MPU_TABLE_PWR_REG

dport_mem_access_dbug0_reg: DPORT_MEM_ACCESS_DBUG0_REG

0x3e8 - DPORT_MEM_ACCESS_DBUG0_REG

dport_mem_access_dbug1_reg: DPORT_MEM_ACCESS_DBUG1_REG

0x3ec - DPORT_MEM_ACCESS_DBUG1_REG

dport_pro_dcache_dbug0_reg: DPORT_PRO_DCACHE_DBUG0_REG

0x3f0 - DPORT_PRO_DCACHE_DBUG0_REG

dport_pro_dcache_dbug1_reg: DPORT_PRO_DCACHE_DBUG1_REG

0x3f4 - DPORT_PRO_DCACHE_DBUG1_REG

dport_pro_dcache_dbug2_reg: DPORT_PRO_DCACHE_DBUG2_REG

0x3f8 - DPORT_PRO_DCACHE_DBUG2_REG

dport_pro_dcache_dbug3_reg: DPORT_PRO_DCACHE_DBUG3_REG

0x3fc - DPORT_PRO_DCACHE_DBUG3_REG

dport_pro_dcache_dbug4_reg: DPORT_PRO_DCACHE_DBUG4_REG

0x400 - DPORT_PRO_DCACHE_DBUG4_REG

dport_pro_dcache_dbug5_reg: DPORT_PRO_DCACHE_DBUG5_REG

0x404 - DPORT_PRO_DCACHE_DBUG5_REG

dport_pro_dcache_dbug6_reg: DPORT_PRO_DCACHE_DBUG6_REG

0x408 - DPORT_PRO_DCACHE_DBUG6_REG

dport_pro_dcache_dbug7_reg: DPORT_PRO_DCACHE_DBUG7_REG

0x40c - DPORT_PRO_DCACHE_DBUG7_REG

dport_pro_dcache_dbug8_reg: DPORT_PRO_DCACHE_DBUG8_REG

0x410 - DPORT_PRO_DCACHE_DBUG8_REG

dport_pro_dcache_dbug9_reg: DPORT_PRO_DCACHE_DBUG9_REG

0x414 - DPORT_PRO_DCACHE_DBUG9_REG

dport_app_dcache_dbug0_reg: DPORT_APP_DCACHE_DBUG0_REG

0x418 - DPORT_APP_DCACHE_DBUG0_REG

dport_app_dcache_dbug1_reg: DPORT_APP_DCACHE_DBUG1_REG

0x41c - DPORT_APP_DCACHE_DBUG1_REG

dport_app_dcache_dbug2_reg: DPORT_APP_DCACHE_DBUG2_REG

0x420 - DPORT_APP_DCACHE_DBUG2_REG

dport_app_dcache_dbug3_reg: DPORT_APP_DCACHE_DBUG3_REG

0x424 - DPORT_APP_DCACHE_DBUG3_REG

dport_app_dcache_dbug4_reg: DPORT_APP_DCACHE_DBUG4_REG

0x428 - DPORT_APP_DCACHE_DBUG4_REG

dport_app_dcache_dbug5_reg: DPORT_APP_DCACHE_DBUG5_REG

0x42c - DPORT_APP_DCACHE_DBUG5_REG

dport_app_dcache_dbug6_reg: DPORT_APP_DCACHE_DBUG6_REG

0x430 - DPORT_APP_DCACHE_DBUG6_REG

dport_app_dcache_dbug7_reg: DPORT_APP_DCACHE_DBUG7_REG

0x434 - DPORT_APP_DCACHE_DBUG7_REG

dport_app_dcache_dbug8_reg: DPORT_APP_DCACHE_DBUG8_REG

0x438 - DPORT_APP_DCACHE_DBUG8_REG

dport_app_dcache_dbug9_reg: DPORT_APP_DCACHE_DBUG9_REG

0x43c - DPORT_APP_DCACHE_DBUG9_REG

dport_pro_cpu_record_ctrl_reg: DPORT_PRO_CPU_RECORD_CTRL_REG

0x440 - DPORT_PRO_CPU_RECORD_CTRL_REG

dport_pro_cpu_record_status_reg: DPORT_PRO_CPU_RECORD_STATUS_REG

0x444 - DPORT_PRO_CPU_RECORD_STATUS_REG

dport_pro_cpu_record_pid_reg: DPORT_PRO_CPU_RECORD_PID_REG

0x448 - DPORT_PRO_CPU_RECORD_PID_REG

dport_pro_cpu_record_pdebuginst_reg: DPORT_PRO_CPU_RECORD_PDEBUGINST_REG

0x44c - DPORT_PRO_CPU_RECORD_PDEBUGINST_REG

dport_pro_cpu_record_pdebugstatus_reg: DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG

0x450 - DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG

dport_pro_cpu_record_pdebugdata_reg: DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG

0x454 - DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG

dport_pro_cpu_record_pdebugpc_reg: DPORT_PRO_CPU_RECORD_PDEBUGPC_REG

0x458 - DPORT_PRO_CPU_RECORD_PDEBUGPC_REG

dport_pro_cpu_record_pdebugls0stat_reg: DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG

0x45c - DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG

dport_pro_cpu_record_pdebugls0addr_reg: DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG

0x460 - DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG

dport_pro_cpu_record_pdebugls0data_reg: DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG

0x464 - DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG

dport_app_cpu_record_ctrl_reg: DPORT_APP_CPU_RECORD_CTRL_REG

0x468 - DPORT_APP_CPU_RECORD_CTRL_REG

dport_app_cpu_record_status_reg: DPORT_APP_CPU_RECORD_STATUS_REG

0x46c - DPORT_APP_CPU_RECORD_STATUS_REG

dport_app_cpu_record_pid_reg: DPORT_APP_CPU_RECORD_PID_REG

0x470 - DPORT_APP_CPU_RECORD_PID_REG

dport_app_cpu_record_pdebuginst_reg: DPORT_APP_CPU_RECORD_PDEBUGINST_REG

0x474 - DPORT_APP_CPU_RECORD_PDEBUGINST_REG

dport_app_cpu_record_pdebugstatus_reg: DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG

0x478 - DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG

dport_app_cpu_record_pdebugdata_reg: DPORT_APP_CPU_RECORD_PDEBUGDATA_REG

0x47c - DPORT_APP_CPU_RECORD_PDEBUGDATA_REG

dport_app_cpu_record_pdebugpc_reg: DPORT_APP_CPU_RECORD_PDEBUGPC_REG

0x480 - DPORT_APP_CPU_RECORD_PDEBUGPC_REG

dport_app_cpu_record_pdebugls0stat_reg: DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG

0x484 - DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG

dport_app_cpu_record_pdebugls0addr_reg: DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG

0x488 - DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG

dport_app_cpu_record_pdebugls0data_reg: DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG

0x48c - DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG

dport_rsa_pd_ctrl_reg: DPORT_RSA_PD_CTRL_REG

0x490 - DPORT_RSA_PD_CTRL_REG

dport_rom_mpu_table0_reg: DPORT_ROM_MPU_TABLE0_REG

0x494 - DPORT_ROM_MPU_TABLE0_REG

dport_rom_mpu_table1_reg: DPORT_ROM_MPU_TABLE1_REG

0x498 - DPORT_ROM_MPU_TABLE1_REG

dport_rom_mpu_table2_reg: DPORT_ROM_MPU_TABLE2_REG

0x49c - DPORT_ROM_MPU_TABLE2_REG

dport_rom_mpu_table3_reg: DPORT_ROM_MPU_TABLE3_REG

0x4a0 - DPORT_ROM_MPU_TABLE3_REG

dport_shrom_mpu_table0_reg: DPORT_SHROM_MPU_TABLE0_REG

0x4a4 - DPORT_SHROM_MPU_TABLE0_REG

dport_shrom_mpu_table1_reg: DPORT_SHROM_MPU_TABLE1_REG

0x4a8 - DPORT_SHROM_MPU_TABLE1_REG

dport_shrom_mpu_table2_reg: DPORT_SHROM_MPU_TABLE2_REG

0x4ac - DPORT_SHROM_MPU_TABLE2_REG

dport_shrom_mpu_table3_reg: DPORT_SHROM_MPU_TABLE3_REG

0x4b0 - DPORT_SHROM_MPU_TABLE3_REG

dport_shrom_mpu_table4_reg: DPORT_SHROM_MPU_TABLE4_REG

0x4b4 - DPORT_SHROM_MPU_TABLE4_REG

dport_shrom_mpu_table5_reg: DPORT_SHROM_MPU_TABLE5_REG

0x4b8 - DPORT_SHROM_MPU_TABLE5_REG

dport_shrom_mpu_table6_reg: DPORT_SHROM_MPU_TABLE6_REG

0x4bc - DPORT_SHROM_MPU_TABLE6_REG

dport_shrom_mpu_table7_reg: DPORT_SHROM_MPU_TABLE7_REG

0x4c0 - DPORT_SHROM_MPU_TABLE7_REG

dport_shrom_mpu_table8_reg: DPORT_SHROM_MPU_TABLE8_REG

0x4c4 - DPORT_SHROM_MPU_TABLE8_REG

dport_shrom_mpu_table9_reg: DPORT_SHROM_MPU_TABLE9_REG

0x4c8 - DPORT_SHROM_MPU_TABLE9_REG

dport_shrom_mpu_table10_reg: DPORT_SHROM_MPU_TABLE10_REG

0x4cc - DPORT_SHROM_MPU_TABLE10_REG

dport_shrom_mpu_table11_reg: DPORT_SHROM_MPU_TABLE11_REG

0x4d0 - DPORT_SHROM_MPU_TABLE11_REG

dport_shrom_mpu_table12_reg: DPORT_SHROM_MPU_TABLE12_REG

0x4d4 - DPORT_SHROM_MPU_TABLE12_REG

dport_shrom_mpu_table13_reg: DPORT_SHROM_MPU_TABLE13_REG

0x4d8 - DPORT_SHROM_MPU_TABLE13_REG

dport_shrom_mpu_table14_reg: DPORT_SHROM_MPU_TABLE14_REG

0x4dc - DPORT_SHROM_MPU_TABLE14_REG

dport_shrom_mpu_table15_reg: DPORT_SHROM_MPU_TABLE15_REG

0x4e0 - DPORT_SHROM_MPU_TABLE15_REG

dport_shrom_mpu_table16_reg: DPORT_SHROM_MPU_TABLE16_REG

0x4e4 - DPORT_SHROM_MPU_TABLE16_REG

dport_shrom_mpu_table17_reg: DPORT_SHROM_MPU_TABLE17_REG

0x4e8 - DPORT_SHROM_MPU_TABLE17_REG

dport_shrom_mpu_table18_reg: DPORT_SHROM_MPU_TABLE18_REG

0x4ec - DPORT_SHROM_MPU_TABLE18_REG

dport_shrom_mpu_table19_reg: DPORT_SHROM_MPU_TABLE19_REG

0x4f0 - DPORT_SHROM_MPU_TABLE19_REG

dport_shrom_mpu_table20_reg: DPORT_SHROM_MPU_TABLE20_REG

0x4f4 - DPORT_SHROM_MPU_TABLE20_REG

dport_shrom_mpu_table21_reg: DPORT_SHROM_MPU_TABLE21_REG

0x4f8 - DPORT_SHROM_MPU_TABLE21_REG

dport_shrom_mpu_table22_reg: DPORT_SHROM_MPU_TABLE22_REG

0x4fc - DPORT_SHROM_MPU_TABLE22_REG

dport_shrom_mpu_table23_reg: DPORT_SHROM_MPU_TABLE23_REG

0x500 - DPORT_SHROM_MPU_TABLE23_REG

dport_immu_table0_reg: DPORT_IMMU_TABLE0_REG

0x504 - DPORT_IMMU_TABLE0_REG

dport_immu_table1_reg: DPORT_IMMU_TABLE1_REG

0x508 - DPORT_IMMU_TABLE1_REG

dport_immu_table2_reg: DPORT_IMMU_TABLE2_REG

0x50c - DPORT_IMMU_TABLE2_REG

dport_immu_table3_reg: DPORT_IMMU_TABLE3_REG

0x510 - DPORT_IMMU_TABLE3_REG

dport_immu_table4_reg: DPORT_IMMU_TABLE4_REG

0x514 - DPORT_IMMU_TABLE4_REG

dport_immu_table5_reg: DPORT_IMMU_TABLE5_REG

0x518 - DPORT_IMMU_TABLE5_REG

dport_immu_table6_reg: DPORT_IMMU_TABLE6_REG

0x51c - DPORT_IMMU_TABLE6_REG

dport_immu_table7_reg: DPORT_IMMU_TABLE7_REG

0x520 - DPORT_IMMU_TABLE7_REG

dport_immu_table8_reg: DPORT_IMMU_TABLE8_REG

0x524 - DPORT_IMMU_TABLE8_REG

dport_immu_table9_reg: DPORT_IMMU_TABLE9_REG

0x528 - DPORT_IMMU_TABLE9_REG

dport_immu_table10_reg: DPORT_IMMU_TABLE10_REG

0x52c - DPORT_IMMU_TABLE10_REG

dport_immu_table11_reg: DPORT_IMMU_TABLE11_REG

0x530 - DPORT_IMMU_TABLE11_REG

dport_immu_table12_reg: DPORT_IMMU_TABLE12_REG

0x534 - DPORT_IMMU_TABLE12_REG

dport_immu_table13_reg: DPORT_IMMU_TABLE13_REG

0x538 - DPORT_IMMU_TABLE13_REG

dport_immu_table14_reg: DPORT_IMMU_TABLE14_REG

0x53c - DPORT_IMMU_TABLE14_REG

dport_immu_table15_reg: DPORT_IMMU_TABLE15_REG

0x540 - DPORT_IMMU_TABLE15_REG

dport_dmmu_table0_reg: DPORT_DMMU_TABLE0_REG

0x544 - DPORT_DMMU_TABLE0_REG

dport_dmmu_table1_reg: DPORT_DMMU_TABLE1_REG

0x548 - DPORT_DMMU_TABLE1_REG

dport_dmmu_table2_reg: DPORT_DMMU_TABLE2_REG

0x54c - DPORT_DMMU_TABLE2_REG

dport_dmmu_table3_reg: DPORT_DMMU_TABLE3_REG

0x550 - DPORT_DMMU_TABLE3_REG

dport_dmmu_table4_reg: DPORT_DMMU_TABLE4_REG

0x554 - DPORT_DMMU_TABLE4_REG

dport_dmmu_table5_reg: DPORT_DMMU_TABLE5_REG

0x558 - DPORT_DMMU_TABLE5_REG

dport_dmmu_table6_reg: DPORT_DMMU_TABLE6_REG

0x55c - DPORT_DMMU_TABLE6_REG

dport_dmmu_table7_reg: DPORT_DMMU_TABLE7_REG

0x560 - DPORT_DMMU_TABLE7_REG

dport_dmmu_table8_reg: DPORT_DMMU_TABLE8_REG

0x564 - DPORT_DMMU_TABLE8_REG

dport_dmmu_table9_reg: DPORT_DMMU_TABLE9_REG

0x568 - DPORT_DMMU_TABLE9_REG

dport_dmmu_table10_reg: DPORT_DMMU_TABLE10_REG

0x56c - DPORT_DMMU_TABLE10_REG

dport_dmmu_table11_reg: DPORT_DMMU_TABLE11_REG

0x570 - DPORT_DMMU_TABLE11_REG

dport_dmmu_table12_reg: DPORT_DMMU_TABLE12_REG

0x574 - DPORT_DMMU_TABLE12_REG

dport_dmmu_table13_reg: DPORT_DMMU_TABLE13_REG

0x578 - DPORT_DMMU_TABLE13_REG

dport_dmmu_table14_reg: DPORT_DMMU_TABLE14_REG

0x57c - DPORT_DMMU_TABLE14_REG

dport_dmmu_table15_reg: DPORT_DMMU_TABLE15_REG

0x580 - DPORT_DMMU_TABLE15_REG

dport_pro_intrusion_ctrl_reg: DPORT_PRO_INTRUSION_CTRL_REG

0x584 - DPORT_PRO_INTRUSION_CTRL_REG

dport_pro_intrusion_status_reg: DPORT_PRO_INTRUSION_STATUS_REG

0x588 - DPORT_PRO_INTRUSION_STATUS_REG

dport_app_intrusion_ctrl_reg: DPORT_APP_INTRUSION_CTRL_REG

0x58c - DPORT_APP_INTRUSION_CTRL_REG

dport_app_intrusion_status_reg: DPORT_APP_INTRUSION_STATUS_REG

0x590 - DPORT_APP_INTRUSION_STATUS_REG

dport_front_end_mem_pd_reg: DPORT_FRONT_END_MEM_PD_REG

0x594 - DPORT_FRONT_END_MEM_PD_REG

dport_mmu_ia_int_en_reg: DPORT_MMU_IA_INT_EN_REG

0x598 - DPORT_MMU_IA_INT_EN_REG

dport_mpu_ia_int_en_reg: DPORT_MPU_IA_INT_EN_REG

0x59c - DPORT_MPU_IA_INT_EN_REG

dport_cache_ia_int_en_reg: DPORT_CACHE_IA_INT_EN_REG

0x5a0 - DPORT_CACHE_IA_INT_EN_REG

dport_secure_boot_ctrl_reg: DPORT_SECURE_BOOT_CTRL_REG

0x5a4 - DPORT_SECURE_BOOT_CTRL_REG

dport_spi_dma_chan_sel_reg: DPORT_SPI_DMA_CHAN_SEL_REG

0x5a8 - DPORT_SPI_DMA_CHAN_SEL_REG

dport_pro_vecbase_ctrl_reg: DPORT_PRO_VECBASE_CTRL_REG

0x5ac - DPORT_PRO_VECBASE_CTRL_REG

dport_pro_vecbase_set_reg: DPORT_PRO_VECBASE_SET_REG

0x5b0 - DPORT_PRO_VECBASE_SET_REG

dport_app_vecbase_ctrl_reg: DPORT_APP_VECBASE_CTRL_REG

0x5b4 - DPORT_APP_VECBASE_CTRL_REG

dport_app_vecbase_set_reg: DPORT_APP_VECBASE_SET_REG

0x5b8 - DPORT_APP_VECBASE_SET_REG

dport_date_reg: DPORT_DATE_REG

0xffc - DPORT_DATE_REG