[−][src]Type Definition esp32::syscon::syscon_saradc_ctrl_reg::R
type R = R<u32, SYSCON_SARADC_CTRL_REG>;
Reader of register SYSCON_SARADC_CTRL_REG
Methods
impl R[src]
pub fn syscon_saradc_data_to_i2s(&self) -> SYSCON_SARADC_DATA_TO_I2S_R[src]
Bit 26 - 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix
pub fn syscon_saradc_data_sar_sel(&self) -> SYSCON_SARADC_DATA_SAR_SEL_R[src]
Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.
pub fn syscon_saradc_sar2_patt_p_clear(
&self
) -> SYSCON_SARADC_SAR2_PATT_P_CLEAR_R[src]
&self
) -> SYSCON_SARADC_SAR2_PATT_P_CLEAR_R
Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL
pub fn syscon_saradc_sar1_patt_p_clear(
&self
) -> SYSCON_SARADC_SAR1_PATT_P_CLEAR_R[src]
&self
) -> SYSCON_SARADC_SAR1_PATT_P_CLEAR_R
Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL
pub fn syscon_saradc_sar2_patt_len(&self) -> SYSCON_SARADC_SAR2_PATT_LEN_R[src]
Bits 19:22 - 0 ~ 15 means length 1 ~ 16
pub fn syscon_saradc_sar1_patt_len(&self) -> SYSCON_SARADC_SAR1_PATT_LEN_R[src]
Bits 15:18 - 0 ~ 15 means length 1 ~ 16
pub fn syscon_saradc_sar_clk_div(&self) -> SYSCON_SARADC_SAR_CLK_DIV_R[src]
Bits 7:14 - SAR clock divider
pub fn syscon_saradc_sar_clk_gated(&self) -> SYSCON_SARADC_SAR_CLK_GATED_R[src]
Bit 6
pub fn syscon_saradc_sar_sel(&self) -> SYSCON_SARADC_SAR_SEL_R[src]
Bit 5 - 0: SAR1 1: SAR2 only work for single SAR mode
pub fn syscon_saradc_work_mode(&self) -> SYSCON_SARADC_WORK_MODE_R[src]
Bits 3:4 - 0: single mode 1: double mode 2: alternate mode
pub fn syscon_saradc_sar2_mux(&self) -> SYSCON_SARADC_SAR2_MUX_R[src]
Bit 2 - 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL
pub fn syscon_saradc_start(&self) -> SYSCON_SARADC_START_R[src]
Bit 1
pub fn syscon_saradc_start_force(&self) -> SYSCON_SARADC_START_FORCE_R[src]
Bit 0