Type Definition esp32::spi::spi_ctrl_reg::W

type W = W<u32, SPI_CTRL_REG>;

Writer for register SPI_CTRL_REG

Methods

impl W

pub fn spi_wr_bit_order(&mut self) -> SPI_WR_BIT_ORDER_W

Bit 26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first

pub fn spi_rd_bit_order(&mut self) -> SPI_RD_BIT_ORDER_W

Bit 25 - In read-data (MISO) phase 1: LSB first 0: MSB first

pub fn spi_fread_qio(&mut self) -> SPI_FREAD_QIO_W

Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.

pub fn spi_fread_dio(&mut self) -> SPI_FREAD_DIO_W

Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.

pub fn spi_wrsr_2b(&mut self) -> SPI_WRSR_2B_W

Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable.

pub fn spi_wp_reg(&mut self) -> SPI_WP_REG_W

Bit 21 - Write protect signal output when SPI is idle. 1: output high 0: output low.

pub fn spi_fread_quad(&mut self) -> SPI_FREAD_QUAD_W

Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable.

pub fn spi_resandres(&mut self) -> SPI_RESANDRES_W

Bit 15 - The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.

pub fn spi_fread_dual(&mut self) -> SPI_FREAD_DUAL_W

Bit 14 - In the read operations read-data phase apply 2 signals. 1: enable 0: disable.

pub fn spi_fastrd_mode(&mut self) -> SPI_FASTRD_MODE_W

Bit 13 - This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.

pub fn spi_wait_flash_idle_en(&mut self) -> SPI_WAIT_FLASH_IDLE_EN_W

Bit 12 - wait flash idle when program flash or erase flash. 1: enable 0: disable.

pub fn spi_tx_crc_en(&mut self) -> SPI_TX_CRC_EN_W

Bit 11 - For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable

pub fn spi_fcs_crc_en(&mut self) -> SPI_FCS_CRC_EN_W

Bit 10 - For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.