Type Definition esp32::spi::spi_cache_sctrl_reg::W

type W = W<u32, SPI_CACHE_SCTRL_REG>;

Writer for register SPI_CACHE_SCTRL_REG

Methods

impl W

pub fn spi_cache_sram_usr_wcmd(&mut self) -> SPI_CACHE_SRAM_USR_WCMD_W

Bit 28 - For SPI0 In the spi sram mode cache write sram for user define command

pub fn spi_sram_addr_bitlen(&mut self) -> SPI_SRAM_ADDR_BITLEN_W

Bits 22:27 - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).

pub fn spi_sram_dummy_cyclelen(&mut self) -> SPI_SRAM_DUMMY_CYCLELEN_W

Bits 14:21 - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).

pub fn spi_sram_bytes_len(&mut self) -> SPI_SRAM_BYTES_LEN_W

Bits 6:13 - For SPI0 In the sram mode it is the byte length of spi read sram data.

pub fn spi_cache_sram_usr_rcmd(&mut self) -> SPI_CACHE_SRAM_USR_RCMD_W

Bit 5 - For SPI0 In the spi sram mode cache read sram for user define command.

pub fn spi_usr_rd_sram_dummy(&mut self) -> SPI_USR_RD_SRAM_DUMMY_W

Bit 4 - For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.

pub fn spi_usr_wr_sram_dummy(&mut self) -> SPI_USR_WR_SRAM_DUMMY_W

Bit 3 - For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.

pub fn spi_usr_sram_qio(&mut self) -> SPI_USR_SRAM_QIO_W

Bit 2 - For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable

pub fn spi_usr_sram_dio(&mut self) -> SPI_USR_SRAM_DIO_W

Bit 1 - For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable