Type Definition esp32::rmt::rmt_int_st_reg::R

type R = R<u32, RMT_INT_ST_REG>;

Reader of register RMT_INT_ST_REG

Methods

impl R

pub fn rmt_ch7_tx_thr_event_int_st(&self) -> RMT_CH7_TX_THR_EVENT_INT_ST_R

Bit 31 - The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.

pub fn rmt_ch6_tx_thr_event_int_st(&self) -> RMT_CH6_TX_THR_EVENT_INT_ST_R

Bit 30 - The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.

pub fn rmt_ch5_tx_thr_event_int_st(&self) -> RMT_CH5_TX_THR_EVENT_INT_ST_R

Bit 29 - The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.

pub fn rmt_ch4_tx_thr_event_int_st(&self) -> RMT_CH4_TX_THR_EVENT_INT_ST_R

Bit 28 - The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.

pub fn rmt_ch3_tx_thr_event_int_st(&self) -> RMT_CH3_TX_THR_EVENT_INT_ST_R

Bit 27 - The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.

pub fn rmt_ch2_tx_thr_event_int_st(&self) -> RMT_CH2_TX_THR_EVENT_INT_ST_R

Bit 26 - The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.

pub fn rmt_ch1_tx_thr_event_int_st(&self) -> RMT_CH1_TX_THR_EVENT_INT_ST_R

Bit 25 - The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.

pub fn rmt_ch0_tx_thr_event_int_st(&self) -> RMT_CH0_TX_THR_EVENT_INT_ST_R

Bit 24 - The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.

pub fn rmt_ch7_err_int_st(&self) -> RMT_CH7_ERR_INT_ST_R

Bit 23 - The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.

pub fn rmt_ch7_rx_end_int_st(&self) -> RMT_CH7_RX_END_INT_ST_R

Bit 22 - The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.

pub fn rmt_ch7_tx_end_int_st(&self) -> RMT_CH7_TX_END_INT_ST_R

Bit 21 - The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.

pub fn rmt_ch6_err_int_st(&self) -> RMT_CH6_ERR_INT_ST_R

Bit 20 - The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.

pub fn rmt_ch6_rx_end_int_st(&self) -> RMT_CH6_RX_END_INT_ST_R

Bit 19 - The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.

pub fn rmt_ch6_tx_end_int_st(&self) -> RMT_CH6_TX_END_INT_ST_R

Bit 18 - The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.

pub fn rmt_ch5_err_int_st(&self) -> RMT_CH5_ERR_INT_ST_R

Bit 17 - The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.

pub fn rmt_ch5_rx_end_int_st(&self) -> RMT_CH5_RX_END_INT_ST_R

Bit 16 - The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.

pub fn rmt_ch5_tx_end_int_st(&self) -> RMT_CH5_TX_END_INT_ST_R

Bit 15 - The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.

pub fn rmt_ch4_err_int_st(&self) -> RMT_CH4_ERR_INT_ST_R

Bit 14 - The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.

pub fn rmt_ch4_rx_end_int_st(&self) -> RMT_CH4_RX_END_INT_ST_R

Bit 13 - The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.

pub fn rmt_ch4_tx_end_int_st(&self) -> RMT_CH4_TX_END_INT_ST_R

Bit 12 - The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.

pub fn rmt_ch3_err_int_st(&self) -> RMT_CH3_ERR_INT_ST_R

Bit 11 - The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.

pub fn rmt_ch3_rx_end_int_st(&self) -> RMT_CH3_RX_END_INT_ST_R

Bit 10 - The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.

pub fn rmt_ch3_tx_end_int_st(&self) -> RMT_CH3_TX_END_INT_ST_R

Bit 9 - The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.

pub fn rmt_ch2_err_int_st(&self) -> RMT_CH2_ERR_INT_ST_R

Bit 8 - The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.

pub fn rmt_ch2_rx_end_int_st(&self) -> RMT_CH2_RX_END_INT_ST_R

Bit 7 - The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.

pub fn rmt_ch2_tx_end_int_st(&self) -> RMT_CH2_TX_END_INT_ST_R

Bit 6 - The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.

pub fn rmt_ch1_err_int_st(&self) -> RMT_CH1_ERR_INT_ST_R

Bit 5 - The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.

pub fn rmt_ch1_rx_end_int_st(&self) -> RMT_CH1_RX_END_INT_ST_R

Bit 4 - The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.

pub fn rmt_ch1_tx_end_int_st(&self) -> RMT_CH1_TX_END_INT_ST_R

Bit 3 - The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.

pub fn rmt_ch0_err_int_st(&self) -> RMT_CH0_ERR_INT_ST_R

Bit 2 - The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.

pub fn rmt_ch0_rx_end_int_st(&self) -> RMT_CH0_RX_END_INT_ST_R

Bit 1 - The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.

pub fn rmt_ch0_tx_end_int_st(&self) -> RMT_CH0_TX_END_INT_ST_R

Bit 0 - The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.