[][src]Type Definition esp32::rmt::rmt_ch7status_reg::R

type R = R<u32, RMT_CH7STATUS_REG>;

Reader of register RMT_CH7STATUS_REG

Methods

impl R[src]

pub fn rmt_status_ch7(&self) -> RMT_STATUS_CH7_R[src]

Bits 0:31 - The status for channel7

pub fn rmt_apb_mem_rd_err_ch7(&self) -> RMT_APB_MEM_RD_ERR_CH7_R[src]

Bit 31 - The apb read memory status bit for channel7 turns to high level when the apb read address exceeds the configuration range.

pub fn rmt_apb_mem_wr_err_ch7(&self) -> RMT_APB_MEM_WR_ERR_CH7_R[src]

Bit 30 - The apb write memory status bit for channel7 turns to high level when the apb write address exceeds the configuration range.

pub fn rmt_mem_empty_ch7(&self) -> RMT_MEM_EMPTY_CH7_R[src]

Bit 29 - The memory empty status bit for channel7. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.

pub fn rmt_mem_full_ch7(&self) -> RMT_MEM_FULL_CH7_R[src]

Bit 28 - The memory full status bit for channel7 turns to high level when mem_waddr_ex is greater than or equal to the configuration range.

pub fn rmt_mem_owner_err_ch7(&self) -> RMT_MEM_OWNER_ERR_CH7_R[src]

Bit 27 - When channel7 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1.

pub fn rmt_state_ch7(&self) -> RMT_STATE_CH7_R[src]

Bits 24:26 - The channel7 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.

pub fn rmt_mem_raddr_ex_ch7(&self) -> RMT_MEM_RADDR_EX_CH7_R[src]

Bits 12:21 - The current memory write address of channel7.

pub fn rmt_mem_waddr_ex_ch7(&self) -> RMT_MEM_WADDR_EX_CH7_R[src]

Bits 0:9 - The current memory read address of channel7.