[][src]Struct esp32::mcpwm::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub mcpwm_clk_cfg_reg: MCPWM_CLK_CFG_REG,
    pub mcpwm_timer0_cfg0_reg: MCPWM_TIMER0_CFG0_REG,
    pub mcpwm_timer0_cfg1_reg: MCPWM_TIMER0_CFG1_REG,
    pub mcpwm_timer0_sync_reg: MCPWM_TIMER0_SYNC_REG,
    pub mcpwm_timer0_status_reg: MCPWM_TIMER0_STATUS_REG,
    pub mcpwm_timer1_cfg0_reg: MCPWM_TIMER1_CFG0_REG,
    pub mcpwm_timer1_cfg1_reg: MCPWM_TIMER1_CFG1_REG,
    pub mcpwm_timer1_sync_reg: MCPWM_TIMER1_SYNC_REG,
    pub mcpwm_timer1_status_reg: MCPWM_TIMER1_STATUS_REG,
    pub mcpwm_timer2_cfg0_reg: MCPWM_TIMER2_CFG0_REG,
    pub mcpwm_timer2_cfg1_reg: MCPWM_TIMER2_CFG1_REG,
    pub mcpwm_timer2_sync_reg: MCPWM_TIMER2_SYNC_REG,
    pub mcpwm_timer2_status_reg: MCPWM_TIMER2_STATUS_REG,
    pub mcpwm_timer_synci_cfg_reg: MCPWM_TIMER_SYNCI_CFG_REG,
    pub mcpwm_operator_timersel_reg: MCPWM_OPERATOR_TIMERSEL_REG,
    pub mcpwm_gen0_stmp_cfg_reg: MCPWM_GEN0_STMP_CFG_REG,
    pub mcpwm_gen0_tstmp_a_reg: MCPWM_GEN0_TSTMP_A_REG,
    pub mcpwm_gen0_tstmp_b_reg: MCPWM_GEN0_TSTMP_B_REG,
    pub mcpwm_gen0_cfg0_reg: MCPWM_GEN0_CFG0_REG,
    pub mcpwm_gen0_force_reg: MCPWM_GEN0_FORCE_REG,
    pub mcpwm_gen0_a_reg: MCPWM_GEN0_A_REG,
    pub mcpwm_gen0_b_reg: MCPWM_GEN0_B_REG,
    pub mcpwm_dt0_cfg_reg: MCPWM_DT0_CFG_REG,
    pub mcpwm_dt0_fed_cfg_reg: MCPWM_DT0_FED_CFG_REG,
    pub mcpwm_dt0_red_cfg_reg: MCPWM_DT0_RED_CFG_REG,
    pub mcpwm_carrier0_cfg_reg: MCPWM_CARRIER0_CFG_REG,
    pub mcpwm_fh0_cfg0_reg: MCPWM_FH0_CFG0_REG,
    pub mcpwm_fh0_cfg1_reg: MCPWM_FH0_CFG1_REG,
    pub mcpwm_fh0_status_reg: MCPWM_FH0_STATUS_REG,
    pub mcpwm_gen1_stmp_cfg_reg: MCPWM_GEN1_STMP_CFG_REG,
    pub mcpwm_gen1_tstmp_a_reg: MCPWM_GEN1_TSTMP_A_REG,
    pub mcpwm_gen1_tstmp_b_reg: MCPWM_GEN1_TSTMP_B_REG,
    pub mcpwm_gen1_cfg0_reg: MCPWM_GEN1_CFG0_REG,
    pub mcpwm_gen1_force_reg: MCPWM_GEN1_FORCE_REG,
    pub mcpwm_gen1_a_reg: MCPWM_GEN1_A_REG,
    pub mcpwm_gen1_b_reg: MCPWM_GEN1_B_REG,
    pub mcpwm_dt1_cfg_reg: MCPWM_DT1_CFG_REG,
    pub mcpwm_dt1_fed_cfg_reg: MCPWM_DT1_FED_CFG_REG,
    pub mcpwm_dt1_red_cfg_reg: MCPWM_DT1_RED_CFG_REG,
    pub mcpwm_carrier1_cfg_reg: MCPWM_CARRIER1_CFG_REG,
    pub mcpwm_fh1_cfg0_reg: MCPWM_FH1_CFG0_REG,
    pub mcpwm_fh1_cfg1_reg: MCPWM_FH1_CFG1_REG,
    pub mcpwm_fh1_status_reg: MCPWM_FH1_STATUS_REG,
    pub mcpwm_gen2_stmp_cfg_reg: MCPWM_GEN2_STMP_CFG_REG,
    pub mcpwm_gen2_tstmp_a_reg: MCPWM_GEN2_TSTMP_A_REG,
    pub mcpwm_gen2_tstmp_b_reg: MCPWM_GEN2_TSTMP_B_REG,
    pub mcpwm_gen2_cfg0_reg: MCPWM_GEN2_CFG0_REG,
    pub mcpwm_gen2_force_reg: MCPWM_GEN2_FORCE_REG,
    pub mcpwm_gen2_a_reg: MCPWM_GEN2_A_REG,
    pub mcpwm_gen2_b_reg: MCPWM_GEN2_B_REG,
    pub mcpwm_dt2_cfg_reg: MCPWM_DT2_CFG_REG,
    pub mcpwm_dt2_fed_cfg_reg: MCPWM_DT2_FED_CFG_REG,
    pub mcpwm_dt2_red_cfg_reg: MCPWM_DT2_RED_CFG_REG,
    pub mcpwm_carrier2_cfg_reg: MCPWM_CARRIER2_CFG_REG,
    pub mcpwm_fh2_cfg0_reg: MCPWM_FH2_CFG0_REG,
    pub mcpwm_fh2_cfg1_reg: MCPWM_FH2_CFG1_REG,
    pub mcpwm_fh2_status_reg: MCPWM_FH2_STATUS_REG,
    pub mcpwm_fault_detect_reg: MCPWM_FAULT_DETECT_REG,
    pub mcpwm_cap_timer_cfg_reg: MCPWM_CAP_TIMER_CFG_REG,
    pub mcpwm_cap_timer_phase_reg: MCPWM_CAP_TIMER_PHASE_REG,
    pub mcpwm_cap_ch0_cfg_reg: MCPWM_CAP_CH0_CFG_REG,
    pub mcpwm_cap_ch1_cfg_reg: MCPWM_CAP_CH1_CFG_REG,
    pub mcpwm_cap_ch2_cfg_reg: MCPWM_CAP_CH2_CFG_REG,
    pub mcpwm_cap_ch0_reg: MCPWM_CAP_CH0_REG,
    pub mcpwm_cap_ch1_reg: MCPWM_CAP_CH1_REG,
    pub mcpwm_cap_ch2_reg: MCPWM_CAP_CH2_REG,
    pub mcpwm_cap_status_reg: MCPWM_CAP_STATUS_REG,
    pub mcpwm_update_cfg_reg: MCPWM_UPDATE_CFG_REG,
    pub mcmcpwm_int_ena_mcpwm_reg: MCMCPWM_INT_ENA_MCPWM_REG,
    pub mcmcpwm_int_raw_mcpwm_reg: MCMCPWM_INT_RAW_MCPWM_REG,
    pub mcmcpwm_int_st_mcpwm_reg: MCMCPWM_INT_ST_MCPWM_REG,
    pub mcmcpwm_int_clr_mcpwm_reg: MCMCPWM_INT_CLR_MCPWM_REG,
    pub mcpwm_clk_reg: MCPWM_CLK_REG,
    pub mcpwm_version_reg: MCPWM_VERSION_REG,
}

Register block

Fields

mcpwm_clk_cfg_reg: MCPWM_CLK_CFG_REG

0x00 - MCPWM_CLK_CFG_REG(i)

mcpwm_timer0_cfg0_reg: MCPWM_TIMER0_CFG0_REG

0x04 - MCPWM_TIMER0_CFG0_REG(i)

mcpwm_timer0_cfg1_reg: MCPWM_TIMER0_CFG1_REG

0x08 - MCPWM_TIMER0_CFG1_REG(i)

mcpwm_timer0_sync_reg: MCPWM_TIMER0_SYNC_REG

0x0c - MCPWM_TIMER0_SYNC_REG(i)

mcpwm_timer0_status_reg: MCPWM_TIMER0_STATUS_REG

0x10 - MCPWM_TIMER0_STATUS_REG(i)

mcpwm_timer1_cfg0_reg: MCPWM_TIMER1_CFG0_REG

0x14 - MCPWM_TIMER1_CFG0_REG(i)

mcpwm_timer1_cfg1_reg: MCPWM_TIMER1_CFG1_REG

0x18 - MCPWM_TIMER1_CFG1_REG(i)

mcpwm_timer1_sync_reg: MCPWM_TIMER1_SYNC_REG

0x1c - MCPWM_TIMER1_SYNC_REG(i)

mcpwm_timer1_status_reg: MCPWM_TIMER1_STATUS_REG

0x20 - MCPWM_TIMER1_STATUS_REG(i)

mcpwm_timer2_cfg0_reg: MCPWM_TIMER2_CFG0_REG

0x24 - MCPWM_TIMER2_CFG0_REG(i)

mcpwm_timer2_cfg1_reg: MCPWM_TIMER2_CFG1_REG

0x28 - MCPWM_TIMER2_CFG1_REG(i)

mcpwm_timer2_sync_reg: MCPWM_TIMER2_SYNC_REG

0x2c - MCPWM_TIMER2_SYNC_REG(i)

mcpwm_timer2_status_reg: MCPWM_TIMER2_STATUS_REG

0x30 - MCPWM_TIMER2_STATUS_REG(i)

mcpwm_timer_synci_cfg_reg: MCPWM_TIMER_SYNCI_CFG_REG

0x34 - MCPWM_TIMER_SYNCI_CFG_REG(i)

mcpwm_operator_timersel_reg: MCPWM_OPERATOR_TIMERSEL_REG

0x38 - MCPWM_OPERATOR_TIMERSEL_REG(i)

mcpwm_gen0_stmp_cfg_reg: MCPWM_GEN0_STMP_CFG_REG

0x3c - MCPWM_GEN0_STMP_CFG_REG(i)

mcpwm_gen0_tstmp_a_reg: MCPWM_GEN0_TSTMP_A_REG

0x40 - MCPWM_GEN0_TSTMP_A_REG(i)

mcpwm_gen0_tstmp_b_reg: MCPWM_GEN0_TSTMP_B_REG

0x44 - MCPWM_GEN0_TSTMP_B_REG(i)

mcpwm_gen0_cfg0_reg: MCPWM_GEN0_CFG0_REG

0x48 - MCPWM_GEN0_CFG0_REG(i)

mcpwm_gen0_force_reg: MCPWM_GEN0_FORCE_REG

0x4c - MCPWM_GEN0_FORCE_REG(i)

mcpwm_gen0_a_reg: MCPWM_GEN0_A_REG

0x50 - MCPWM_GEN0_A_REG(i)

mcpwm_gen0_b_reg: MCPWM_GEN0_B_REG

0x54 - MCPWM_GEN0_B_REG(i)

mcpwm_dt0_cfg_reg: MCPWM_DT0_CFG_REG

0x58 - MCPWM_DT0_CFG_REG(i)

mcpwm_dt0_fed_cfg_reg: MCPWM_DT0_FED_CFG_REG

0x5c - MCPWM_DT0_FED_CFG_REG(i)

mcpwm_dt0_red_cfg_reg: MCPWM_DT0_RED_CFG_REG

0x60 - MCPWM_DT0_RED_CFG_REG(i)

mcpwm_carrier0_cfg_reg: MCPWM_CARRIER0_CFG_REG

0x64 - MCPWM_CARRIER0_CFG_REG(i)

mcpwm_fh0_cfg0_reg: MCPWM_FH0_CFG0_REG

0x68 - MCPWM_FH0_CFG0_REG(i)

mcpwm_fh0_cfg1_reg: MCPWM_FH0_CFG1_REG

0x6c - MCPWM_FH0_CFG1_REG(i)

mcpwm_fh0_status_reg: MCPWM_FH0_STATUS_REG

0x70 - MCPWM_FH0_STATUS_REG(i)

mcpwm_gen1_stmp_cfg_reg: MCPWM_GEN1_STMP_CFG_REG

0x74 - MCPWM_GEN1_STMP_CFG_REG(i)

mcpwm_gen1_tstmp_a_reg: MCPWM_GEN1_TSTMP_A_REG

0x78 - MCPWM_GEN1_TSTMP_A_REG(i)

mcpwm_gen1_tstmp_b_reg: MCPWM_GEN1_TSTMP_B_REG

0x7c - MCPWM_GEN1_TSTMP_B_REG(i)

mcpwm_gen1_cfg0_reg: MCPWM_GEN1_CFG0_REG

0x80 - MCPWM_GEN1_CFG0_REG(i)

mcpwm_gen1_force_reg: MCPWM_GEN1_FORCE_REG

0x84 - MCPWM_GEN1_FORCE_REG(i)

mcpwm_gen1_a_reg: MCPWM_GEN1_A_REG

0x88 - MCPWM_GEN1_A_REG(i)

mcpwm_gen1_b_reg: MCPWM_GEN1_B_REG

0x8c - MCPWM_GEN1_B_REG(i)

mcpwm_dt1_cfg_reg: MCPWM_DT1_CFG_REG

0x90 - MCPWM_DT1_CFG_REG(i)

mcpwm_dt1_fed_cfg_reg: MCPWM_DT1_FED_CFG_REG

0x94 - MCPWM_DT1_FED_CFG_REG(i)

mcpwm_dt1_red_cfg_reg: MCPWM_DT1_RED_CFG_REG

0x98 - MCPWM_DT1_RED_CFG_REG(i)

mcpwm_carrier1_cfg_reg: MCPWM_CARRIER1_CFG_REG

0x9c - MCPWM_CARRIER1_CFG_REG(i)

mcpwm_fh1_cfg0_reg: MCPWM_FH1_CFG0_REG

0xa0 - MCPWM_FH1_CFG0_REG(i)

mcpwm_fh1_cfg1_reg: MCPWM_FH1_CFG1_REG

0xa4 - MCPWM_FH1_CFG1_REG(i)

mcpwm_fh1_status_reg: MCPWM_FH1_STATUS_REG

0xa8 - MCPWM_FH1_STATUS_REG(i)

mcpwm_gen2_stmp_cfg_reg: MCPWM_GEN2_STMP_CFG_REG

0xac - MCPWM_GEN2_STMP_CFG_REG(i)

mcpwm_gen2_tstmp_a_reg: MCPWM_GEN2_TSTMP_A_REG

0xb0 - MCPWM_GEN2_TSTMP_A_REG(i)

mcpwm_gen2_tstmp_b_reg: MCPWM_GEN2_TSTMP_B_REG

0xb4 - MCPWM_GEN2_TSTMP_B_REG(i)

mcpwm_gen2_cfg0_reg: MCPWM_GEN2_CFG0_REG

0xb8 - MCPWM_GEN2_CFG0_REG(i)

mcpwm_gen2_force_reg: MCPWM_GEN2_FORCE_REG

0xbc - MCPWM_GEN2_FORCE_REG(i)

mcpwm_gen2_a_reg: MCPWM_GEN2_A_REG

0xc0 - MCPWM_GEN2_A_REG(i)

mcpwm_gen2_b_reg: MCPWM_GEN2_B_REG

0xc4 - MCPWM_GEN2_B_REG(i)

mcpwm_dt2_cfg_reg: MCPWM_DT2_CFG_REG

0xc8 - MCPWM_DT2_CFG_REG(i)

mcpwm_dt2_fed_cfg_reg: MCPWM_DT2_FED_CFG_REG

0xcc - MCPWM_DT2_FED_CFG_REG(i)

mcpwm_dt2_red_cfg_reg: MCPWM_DT2_RED_CFG_REG

0xd0 - MCPWM_DT2_RED_CFG_REG(i)

mcpwm_carrier2_cfg_reg: MCPWM_CARRIER2_CFG_REG

0xd4 - MCPWM_CARRIER2_CFG_REG(i)

mcpwm_fh2_cfg0_reg: MCPWM_FH2_CFG0_REG

0xd8 - MCPWM_FH2_CFG0_REG(i)

mcpwm_fh2_cfg1_reg: MCPWM_FH2_CFG1_REG

0xdc - MCPWM_FH2_CFG1_REG(i)

mcpwm_fh2_status_reg: MCPWM_FH2_STATUS_REG

0xe0 - MCPWM_FH2_STATUS_REG(i)

mcpwm_fault_detect_reg: MCPWM_FAULT_DETECT_REG

0xe4 - MCPWM_FAULT_DETECT_REG(i)

mcpwm_cap_timer_cfg_reg: MCPWM_CAP_TIMER_CFG_REG

0xe8 - MCPWM_CAP_TIMER_CFG_REG(i)

mcpwm_cap_timer_phase_reg: MCPWM_CAP_TIMER_PHASE_REG

0xec - MCPWM_CAP_TIMER_PHASE_REG(i)

mcpwm_cap_ch0_cfg_reg: MCPWM_CAP_CH0_CFG_REG

0xf0 - MCPWM_CAP_CH0_CFG_REG(i)

mcpwm_cap_ch1_cfg_reg: MCPWM_CAP_CH1_CFG_REG

0xf4 - MCPWM_CAP_CH1_CFG_REG(i)

mcpwm_cap_ch2_cfg_reg: MCPWM_CAP_CH2_CFG_REG

0xf8 - MCPWM_CAP_CH2_CFG_REG(i)

mcpwm_cap_ch0_reg: MCPWM_CAP_CH0_REG

0xfc - MCPWM_CAP_CH0_REG(i)

mcpwm_cap_ch1_reg: MCPWM_CAP_CH1_REG

0x100 - MCPWM_CAP_CH1_REG(i)

mcpwm_cap_ch2_reg: MCPWM_CAP_CH2_REG

0x104 - MCPWM_CAP_CH2_REG(i)

mcpwm_cap_status_reg: MCPWM_CAP_STATUS_REG

0x108 - MCPWM_CAP_STATUS_REG(i)

mcpwm_update_cfg_reg: MCPWM_UPDATE_CFG_REG

0x10c - MCPWM_UPDATE_CFG_REG(i)

mcmcpwm_int_ena_mcpwm_reg: MCMCPWM_INT_ENA_MCPWM_REG

0x110 - MCMCPWM_INT_ENA_MCPWM_REG(i)

mcmcpwm_int_raw_mcpwm_reg: MCMCPWM_INT_RAW_MCPWM_REG

0x114 - MCMCPWM_INT_RAW_MCPWM_REG(i)

mcmcpwm_int_st_mcpwm_reg: MCMCPWM_INT_ST_MCPWM_REG

0x118 - MCMCPWM_INT_ST_MCPWM_REG(i)

mcmcpwm_int_clr_mcpwm_reg: MCMCPWM_INT_CLR_MCPWM_REG

0x11c - MCMCPWM_INT_CLR_MCPWM_REG(i)

mcpwm_clk_reg: MCPWM_CLK_REG

0x120 - MCPWM_CLK_REG(i)

mcpwm_version_reg: MCPWM_VERSION_REG

0x124 - MCPWM_VERSION_REG(i)

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