[][src]Type Definition esp32::mcpwm::mcpwm_fault_detect_reg::R

type R = R<u32, MCPWM_FAULT_DETECT_REG>;

Reader of register MCPWM_FAULT_DETECT_REG

Methods

impl R[src]

pub fn mcpwm_event_f2(&self) -> MCPWM_EVENT_F2_R[src]

Bit 8 - Set and reset by hardware. If set event_f2 is on going

pub fn mcpwm_event_f1(&self) -> MCPWM_EVENT_F1_R[src]

Bit 7 - Set and reset by hardware. If set event_f1 is on going

pub fn mcpwm_event_f0(&self) -> MCPWM_EVENT_F0_R[src]

Bit 6 - Set and reset by hardware. If set event_f0 is on going

pub fn mcpwm_f2_pole(&self) -> MCPWM_F2_POLE_R[src]

Bit 5 - Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high

pub fn mcpwm_f1_pole(&self) -> MCPWM_F1_POLE_R[src]

Bit 4 - Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high

pub fn mcpwm_f0_pole(&self) -> MCPWM_F0_POLE_R[src]

Bit 3 - Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high

pub fn mcpwm_f2_en(&self) -> MCPWM_F2_EN_R[src]

Bit 2 - Set to enable generation of event_f2

pub fn mcpwm_f1_en(&self) -> MCPWM_F1_EN_R[src]

Bit 1 - Set to enable generation of event_f1

pub fn mcpwm_f0_en(&self) -> MCPWM_F0_EN_R[src]

Bit 0 - Set to enable generation of event_f0