[−][src]Type Definition esp32::mcpwm::mcpwm_dt1_cfg_reg::W
type W = W<u32, MCPWM_DT1_CFG_REG>;
Writer for register MCPWM_DT1_CFG_REG
Methods
impl W[src]
pub fn mcpwm_dt1_clk_sel(&mut self) -> MCPWM_DT1_CLK_SEL_W[src]
Bit 17 - Dead time generator 1 clock selection. 0: PWM_clk 1: PT_clk
pub fn mcpwm_dt1_b_outbypass(&mut self) -> MCPWM_DT1_B_OUTBYPASS_W[src]
Bit 16 - S0 in documentation
pub fn mcpwm_dt1_a_outbypass(&mut self) -> MCPWM_DT1_A_OUTBYPASS_W[src]
Bit 15 - S1 in documentation
pub fn mcpwm_dt1_fed_outinvert(&mut self) -> MCPWM_DT1_FED_OUTINVERT_W[src]
Bit 14 - S3 in documentation
pub fn mcpwm_dt1_red_outinvert(&mut self) -> MCPWM_DT1_RED_OUTINVERT_W[src]
Bit 13 - S2 in documentation
pub fn mcpwm_dt1_fed_insel(&mut self) -> MCPWM_DT1_FED_INSEL_W[src]
Bit 12 - S5 in documentation
pub fn mcpwm_dt1_red_insel(&mut self) -> MCPWM_DT1_RED_INSEL_W[src]
Bit 11 - S4 in documentation
pub fn mcpwm_dt1_b_outswap(&mut self) -> MCPWM_DT1_B_OUTSWAP_W[src]
Bit 10 - S7 in documentation
pub fn mcpwm_dt1_a_outswap(&mut self) -> MCPWM_DT1_A_OUTSWAP_W[src]
Bit 9 - S6 in documentation
pub fn mcpwm_dt1_deb_mode(&mut self) -> MCPWM_DT1_DEB_MODE_W[src]
Bit 8 - S8 in documentation dual-edge B mode 0: FED/RED take effect on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode
pub fn mcpwm_dt1_red_upmethod(&mut self) -> MCPWM_DT1_RED_UPMETHOD_W[src]
Bits 4:7 - Update method for RED (rising edge delay) active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update
pub fn mcpwm_dt1_fed_upmethod(&mut self) -> MCPWM_DT1_FED_UPMETHOD_W[src]
Bits 0:3 - Update method for FED (falling edge delay) active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update