[][src]Struct esp32::efuse::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub efuse_blk0_rdata0_reg: EFUSE_BLK0_RDATA0_REG,
    pub efuse_blk0_rdata1_reg: EFUSE_BLK0_RDATA1_REG,
    pub efuse_blk0_rdata2_reg: EFUSE_BLK0_RDATA2_REG,
    pub efuse_blk0_rdata3_reg: EFUSE_BLK0_RDATA3_REG,
    pub efuse_blk0_rdata4_reg: EFUSE_BLK0_RDATA4_REG,
    pub efuse_blk0_rdata5_reg: EFUSE_BLK0_RDATA5_REG,
    pub efuse_blk0_rdata6_reg: EFUSE_BLK0_RDATA6_REG,
    pub efuse_blk0_wdata0_reg: EFUSE_BLK0_WDATA0_REG,
    pub efuse_blk0_wdata1_reg: EFUSE_BLK0_WDATA1_REG,
    pub efuse_blk0_wdata2_reg: EFUSE_BLK0_WDATA2_REG,
    pub efuse_blk0_wdata3_reg: EFUSE_BLK0_WDATA3_REG,
    pub efuse_blk0_wdata4_reg: EFUSE_BLK0_WDATA4_REG,
    pub efuse_blk0_wdata5_reg: EFUSE_BLK0_WDATA5_REG,
    pub efuse_blk0_wdata6_reg: EFUSE_BLK0_WDATA6_REG,
    pub efuse_blk1_rdata0_reg: EFUSE_BLK1_RDATA0_REG,
    pub efuse_blk1_rdata1_reg: EFUSE_BLK1_RDATA1_REG,
    pub efuse_blk1_rdata2_reg: EFUSE_BLK1_RDATA2_REG,
    pub efuse_blk1_rdata3_reg: EFUSE_BLK1_RDATA3_REG,
    pub efuse_blk1_rdata4_reg: EFUSE_BLK1_RDATA4_REG,
    pub efuse_blk1_rdata5_reg: EFUSE_BLK1_RDATA5_REG,
    pub efuse_blk1_rdata6_reg: EFUSE_BLK1_RDATA6_REG,
    pub efuse_blk1_rdata7_reg: EFUSE_BLK1_RDATA7_REG,
    pub efuse_blk2_rdata0_reg: EFUSE_BLK2_RDATA0_REG,
    pub efuse_blk2_rdata1_reg: EFUSE_BLK2_RDATA1_REG,
    pub efuse_blk2_rdata2_reg: EFUSE_BLK2_RDATA2_REG,
    pub efuse_blk2_rdata3_reg: EFUSE_BLK2_RDATA3_REG,
    pub efuse_blk2_rdata4_reg: EFUSE_BLK2_RDATA4_REG,
    pub efuse_blk2_rdata5_reg: EFUSE_BLK2_RDATA5_REG,
    pub efuse_blk2_rdata6_reg: EFUSE_BLK2_RDATA6_REG,
    pub efuse_blk2_rdata7_reg: EFUSE_BLK2_RDATA7_REG,
    pub efuse_blk3_rdata0_reg: EFUSE_BLK3_RDATA0_REG,
    pub efuse_blk3_rdata1_reg: EFUSE_BLK3_RDATA1_REG,
    pub efuse_blk3_rdata2_reg: EFUSE_BLK3_RDATA2_REG,
    pub efuse_blk3_rdata3_reg: EFUSE_BLK3_RDATA3_REG,
    pub efuse_blk3_rdata4_reg: EFUSE_BLK3_RDATA4_REG,
    pub efuse_blk3_rdata5_reg: EFUSE_BLK3_RDATA5_REG,
    pub efuse_blk3_rdata6_reg: EFUSE_BLK3_RDATA6_REG,
    pub efuse_blk3_rdata7_reg: EFUSE_BLK3_RDATA7_REG,
    pub efuse_blk1_wdata0_reg: EFUSE_BLK1_WDATA0_REG,
    pub efuse_blk1_wdata1_reg: EFUSE_BLK1_WDATA1_REG,
    pub efuse_blk1_wdata2_reg: EFUSE_BLK1_WDATA2_REG,
    pub efuse_blk1_wdata3_reg: EFUSE_BLK1_WDATA3_REG,
    pub efuse_blk1_wdata4_reg: EFUSE_BLK1_WDATA4_REG,
    pub efuse_blk1_wdata5_reg: EFUSE_BLK1_WDATA5_REG,
    pub efuse_blk1_wdata6_reg: EFUSE_BLK1_WDATA6_REG,
    pub efuse_blk1_wdata7_reg: EFUSE_BLK1_WDATA7_REG,
    pub efuse_blk2_wdata0_reg: EFUSE_BLK2_WDATA0_REG,
    pub efuse_blk2_wdata1_reg: EFUSE_BLK2_WDATA1_REG,
    pub efuse_blk2_wdata2_reg: EFUSE_BLK2_WDATA2_REG,
    pub efuse_blk2_wdata3_reg: EFUSE_BLK2_WDATA3_REG,
    pub efuse_blk2_wdata4_reg: EFUSE_BLK2_WDATA4_REG,
    pub efuse_blk2_wdata5_reg: EFUSE_BLK2_WDATA5_REG,
    pub efuse_blk2_wdata6_reg: EFUSE_BLK2_WDATA6_REG,
    pub efuse_blk2_wdata7_reg: EFUSE_BLK2_WDATA7_REG,
    pub efuse_blk3_wdata0_reg: EFUSE_BLK3_WDATA0_REG,
    pub efuse_blk3_wdata1_reg: EFUSE_BLK3_WDATA1_REG,
    pub efuse_blk3_wdata2_reg: EFUSE_BLK3_WDATA2_REG,
    pub efuse_blk3_wdata3_reg: EFUSE_BLK3_WDATA3_REG,
    pub efuse_blk3_wdata4_reg: EFUSE_BLK3_WDATA4_REG,
    pub efuse_blk3_wdata5_reg: EFUSE_BLK3_WDATA5_REG,
    pub efuse_blk3_wdata6_reg: EFUSE_BLK3_WDATA6_REG,
    pub efuse_blk3_wdata7_reg: EFUSE_BLK3_WDATA7_REG,
    pub efuse_clk_reg: EFUSE_CLK_REG,
    pub efuse_conf_reg: EFUSE_CONF_REG,
    pub efuse_status_reg: EFUSE_STATUS_REG,
    pub efuse_cmd_reg: EFUSE_CMD_REG,
    pub efuse_int_raw_reg: EFUSE_INT_RAW_REG,
    pub efuse_int_st_reg: EFUSE_INT_ST_REG,
    pub efuse_int_ena_reg: EFUSE_INT_ENA_REG,
    pub efuse_int_clr_reg: EFUSE_INT_CLR_REG,
    pub efuse_dac_conf_reg: EFUSE_DAC_CONF_REG,
    pub efuse_dec_status_reg: EFUSE_DEC_STATUS_REG,
    pub efuse_date_reg: EFUSE_DATE_REG,
    // some fields omitted
}

Register block

Fields

efuse_blk0_rdata0_reg: EFUSE_BLK0_RDATA0_REG

0x00 - EFUSE_BLK0_RDATA0_REG

efuse_blk0_rdata1_reg: EFUSE_BLK0_RDATA1_REG

0x04 - EFUSE_BLK0_RDATA1_REG

efuse_blk0_rdata2_reg: EFUSE_BLK0_RDATA2_REG

0x08 - EFUSE_BLK0_RDATA2_REG

efuse_blk0_rdata3_reg: EFUSE_BLK0_RDATA3_REG

0x0c - EFUSE_BLK0_RDATA3_REG

efuse_blk0_rdata4_reg: EFUSE_BLK0_RDATA4_REG

0x10 - EFUSE_BLK0_RDATA4_REG

efuse_blk0_rdata5_reg: EFUSE_BLK0_RDATA5_REG

0x14 - EFUSE_BLK0_RDATA5_REG

efuse_blk0_rdata6_reg: EFUSE_BLK0_RDATA6_REG

0x18 - EFUSE_BLK0_RDATA6_REG

efuse_blk0_wdata0_reg: EFUSE_BLK0_WDATA0_REG

0x1c - EFUSE_BLK0_WDATA0_REG

efuse_blk0_wdata1_reg: EFUSE_BLK0_WDATA1_REG

0x20 - EFUSE_BLK0_WDATA1_REG

efuse_blk0_wdata2_reg: EFUSE_BLK0_WDATA2_REG

0x24 - EFUSE_BLK0_WDATA2_REG

efuse_blk0_wdata3_reg: EFUSE_BLK0_WDATA3_REG

0x28 - EFUSE_BLK0_WDATA3_REG

efuse_blk0_wdata4_reg: EFUSE_BLK0_WDATA4_REG

0x2c - EFUSE_BLK0_WDATA4_REG

efuse_blk0_wdata5_reg: EFUSE_BLK0_WDATA5_REG

0x30 - EFUSE_BLK0_WDATA5_REG

efuse_blk0_wdata6_reg: EFUSE_BLK0_WDATA6_REG

0x34 - EFUSE_BLK0_WDATA6_REG

efuse_blk1_rdata0_reg: EFUSE_BLK1_RDATA0_REG

0x38 - EFUSE_BLK1_RDATA0_REG

efuse_blk1_rdata1_reg: EFUSE_BLK1_RDATA1_REG

0x3c - EFUSE_BLK1_RDATA1_REG

efuse_blk1_rdata2_reg: EFUSE_BLK1_RDATA2_REG

0x40 - EFUSE_BLK1_RDATA2_REG

efuse_blk1_rdata3_reg: EFUSE_BLK1_RDATA3_REG

0x44 - EFUSE_BLK1_RDATA3_REG

efuse_blk1_rdata4_reg: EFUSE_BLK1_RDATA4_REG

0x48 - EFUSE_BLK1_RDATA4_REG

efuse_blk1_rdata5_reg: EFUSE_BLK1_RDATA5_REG

0x4c - EFUSE_BLK1_RDATA5_REG

efuse_blk1_rdata6_reg: EFUSE_BLK1_RDATA6_REG

0x50 - EFUSE_BLK1_RDATA6_REG

efuse_blk1_rdata7_reg: EFUSE_BLK1_RDATA7_REG

0x54 - EFUSE_BLK1_RDATA7_REG

efuse_blk2_rdata0_reg: EFUSE_BLK2_RDATA0_REG

0x58 - EFUSE_BLK2_RDATA0_REG

efuse_blk2_rdata1_reg: EFUSE_BLK2_RDATA1_REG

0x5c - EFUSE_BLK2_RDATA1_REG

efuse_blk2_rdata2_reg: EFUSE_BLK2_RDATA2_REG

0x60 - EFUSE_BLK2_RDATA2_REG

efuse_blk2_rdata3_reg: EFUSE_BLK2_RDATA3_REG

0x64 - EFUSE_BLK2_RDATA3_REG

efuse_blk2_rdata4_reg: EFUSE_BLK2_RDATA4_REG

0x68 - EFUSE_BLK2_RDATA4_REG

efuse_blk2_rdata5_reg: EFUSE_BLK2_RDATA5_REG

0x6c - EFUSE_BLK2_RDATA5_REG

efuse_blk2_rdata6_reg: EFUSE_BLK2_RDATA6_REG

0x70 - EFUSE_BLK2_RDATA6_REG

efuse_blk2_rdata7_reg: EFUSE_BLK2_RDATA7_REG

0x74 - EFUSE_BLK2_RDATA7_REG

efuse_blk3_rdata0_reg: EFUSE_BLK3_RDATA0_REG

0x78 - EFUSE_BLK3_RDATA0_REG

efuse_blk3_rdata1_reg: EFUSE_BLK3_RDATA1_REG

0x7c - EFUSE_BLK3_RDATA1_REG

efuse_blk3_rdata2_reg: EFUSE_BLK3_RDATA2_REG

0x80 - EFUSE_BLK3_RDATA2_REG

efuse_blk3_rdata3_reg: EFUSE_BLK3_RDATA3_REG

0x84 - EFUSE_BLK3_RDATA3_REG

efuse_blk3_rdata4_reg: EFUSE_BLK3_RDATA4_REG

0x88 - EFUSE_BLK3_RDATA4_REG

efuse_blk3_rdata5_reg: EFUSE_BLK3_RDATA5_REG

0x8c - EFUSE_BLK3_RDATA5_REG

efuse_blk3_rdata6_reg: EFUSE_BLK3_RDATA6_REG

0x90 - EFUSE_BLK3_RDATA6_REG

efuse_blk3_rdata7_reg: EFUSE_BLK3_RDATA7_REG

0x94 - EFUSE_BLK3_RDATA7_REG

efuse_blk1_wdata0_reg: EFUSE_BLK1_WDATA0_REG

0x98 - EFUSE_BLK1_WDATA0_REG

efuse_blk1_wdata1_reg: EFUSE_BLK1_WDATA1_REG

0x9c - EFUSE_BLK1_WDATA1_REG

efuse_blk1_wdata2_reg: EFUSE_BLK1_WDATA2_REG

0xa0 - EFUSE_BLK1_WDATA2_REG

efuse_blk1_wdata3_reg: EFUSE_BLK1_WDATA3_REG

0xa4 - EFUSE_BLK1_WDATA3_REG

efuse_blk1_wdata4_reg: EFUSE_BLK1_WDATA4_REG

0xa8 - EFUSE_BLK1_WDATA4_REG

efuse_blk1_wdata5_reg: EFUSE_BLK1_WDATA5_REG

0xac - EFUSE_BLK1_WDATA5_REG

efuse_blk1_wdata6_reg: EFUSE_BLK1_WDATA6_REG

0xb0 - EFUSE_BLK1_WDATA6_REG

efuse_blk1_wdata7_reg: EFUSE_BLK1_WDATA7_REG

0xb4 - EFUSE_BLK1_WDATA7_REG

efuse_blk2_wdata0_reg: EFUSE_BLK2_WDATA0_REG

0xb8 - EFUSE_BLK2_WDATA0_REG

efuse_blk2_wdata1_reg: EFUSE_BLK2_WDATA1_REG

0xbc - EFUSE_BLK2_WDATA1_REG

efuse_blk2_wdata2_reg: EFUSE_BLK2_WDATA2_REG

0xc0 - EFUSE_BLK2_WDATA2_REG

efuse_blk2_wdata3_reg: EFUSE_BLK2_WDATA3_REG

0xc4 - EFUSE_BLK2_WDATA3_REG

efuse_blk2_wdata4_reg: EFUSE_BLK2_WDATA4_REG

0xc8 - EFUSE_BLK2_WDATA4_REG

efuse_blk2_wdata5_reg: EFUSE_BLK2_WDATA5_REG

0xcc - EFUSE_BLK2_WDATA5_REG

efuse_blk2_wdata6_reg: EFUSE_BLK2_WDATA6_REG

0xd0 - EFUSE_BLK2_WDATA6_REG

efuse_blk2_wdata7_reg: EFUSE_BLK2_WDATA7_REG

0xd4 - EFUSE_BLK2_WDATA7_REG

efuse_blk3_wdata0_reg: EFUSE_BLK3_WDATA0_REG

0xd8 - EFUSE_BLK3_WDATA0_REG

efuse_blk3_wdata1_reg: EFUSE_BLK3_WDATA1_REG

0xdc - EFUSE_BLK3_WDATA1_REG

efuse_blk3_wdata2_reg: EFUSE_BLK3_WDATA2_REG

0xe0 - EFUSE_BLK3_WDATA2_REG

efuse_blk3_wdata3_reg: EFUSE_BLK3_WDATA3_REG

0xe4 - EFUSE_BLK3_WDATA3_REG

efuse_blk3_wdata4_reg: EFUSE_BLK3_WDATA4_REG

0xe8 - EFUSE_BLK3_WDATA4_REG

efuse_blk3_wdata5_reg: EFUSE_BLK3_WDATA5_REG

0xec - EFUSE_BLK3_WDATA5_REG

efuse_blk3_wdata6_reg: EFUSE_BLK3_WDATA6_REG

0xf0 - EFUSE_BLK3_WDATA6_REG

efuse_blk3_wdata7_reg: EFUSE_BLK3_WDATA7_REG

0xf4 - EFUSE_BLK3_WDATA7_REG

efuse_clk_reg: EFUSE_CLK_REG

0xf8 - EFUSE_CLK_REG

efuse_conf_reg: EFUSE_CONF_REG

0xfc - EFUSE_CONF_REG

efuse_status_reg: EFUSE_STATUS_REG

0x100 - EFUSE_STATUS_REG

efuse_cmd_reg: EFUSE_CMD_REG

0x104 - EFUSE_CMD_REG

efuse_int_raw_reg: EFUSE_INT_RAW_REG

0x108 - EFUSE_INT_RAW_REG

efuse_int_st_reg: EFUSE_INT_ST_REG

0x10c - EFUSE_INT_ST_REG

efuse_int_ena_reg: EFUSE_INT_ENA_REG

0x110 - EFUSE_INT_ENA_REG

efuse_int_clr_reg: EFUSE_INT_CLR_REG

0x114 - EFUSE_INT_CLR_REG

efuse_dac_conf_reg: EFUSE_DAC_CONF_REG

0x118 - EFUSE_DAC_CONF_REG

efuse_dec_status_reg: EFUSE_DEC_STATUS_REG

0x11c - EFUSE_DEC_STATUS_REG

efuse_date_reg: EFUSE_DATE_REG

0x1fc - EFUSE_DATE_REG

Auto Trait Implementations

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    T: 'static + ?Sized
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    T: ?Sized
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    T: ?Sized
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impl<T> From<T> for T[src]

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    U: From<T>, 
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    U: Into<T>, 
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    U: TryFrom<T>, 
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