[−][src]Type Definition esp32::efuse::efuse_blk0_rdata3_reg::W

type W = W<u32, EFUSE_BLK0_RDATA3_REG>;

Writer for register EFUSE_BLK0_RDATA3_REG

Methods

`impl W`[src]

`pub fn efuse_rd_chip_ver_rev1(&mut self) -> EFUSE_RD_CHIP_VER_REV1_W`[src]

Bit 15 - bit is set to 1 for rev1 silicon

`pub fn efuse_rd_chip_cpu_freq_rated(&mut self) -> EFUSE_RD_CHIP_CPU_FREQ_RATED_W`[src]

Bit 13 - If set, the ESP32's maximum CPU frequency has been rated

`pub fn efuse_rd_chip_cpu_freq_low(&mut self) -> EFUSE_RD_CHIP_CPU_FREQ_LOW_W`[src]

Bit 12 - If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise

`pub fn efuse_rd_chip_ver_pkg(&mut self) -> EFUSE_RD_CHIP_VER_PKG_W`[src]

Bits 9:11 - chip package

`pub fn efuse_rd_spi_pad_config_hd(&mut self) -> EFUSE_RD_SPI_PAD_CONFIG_HD_W`[src]

Bits 4:8 - read for SPI_pad_config_hd

`pub fn efuse_rd_chip_ver_dis_cache(&mut self) -> EFUSE_RD_CHIP_VER_DIS_CACHE_W`[src]

Bit 3

`pub fn efuse_rd_chip_ver_32pad(&mut self) -> EFUSE_RD_CHIP_VER_32PAD_W`[src]

Bit 2

`pub fn efuse_rd_chip_ver_dis_bt(&mut self) -> EFUSE_RD_CHIP_VER_DIS_BT_W`[src]

Bit 1

`pub fn efuse_rd_chip_ver_dis_app_cpu( &mut self ) -> EFUSE_RD_CHIP_VER_DIS_APP_CPU_W`[src]

Bit 0