Struct esp32_hal::pac::spi0::user::W

pub struct W(_);

Register USER writer

Implementations

impl W

pub fn doutdin(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 0>

Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable.

pub fn cs_hold(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 4>

Bit 4 - spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.

pub fn cs_setup(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 5>

Bit 5 - spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.

pub fn ck_i_edge(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 6>

Bit 6 - In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.

pub fn ck_out_edge(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 7>

Bit 7 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.

pub fn rd_byte_order(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 10>

Bit 10 - In read-data (MISO) phase 1: big-endian 0: little_endian

pub fn wr_byte_order(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 11>

Bit 11 - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian

pub fn fwrite_dual(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 12>

Bit 12 - In the write operations read-data phase apply 2 signals

pub fn fwrite_quad(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 13>

Bit 13 - In the write operations read-data phase apply 4 signals

pub fn fwrite_dio(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 14>

Bit 14 - In the write operations address phase and read-data phase apply 2 signals.

pub fn fwrite_qio(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 15>

Bit 15 - In the write operations address phase and read-data phase apply 4 signals.

pub fn sio(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 16>

Bit 16 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.

pub fn usr_hold_pol(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 17>

Bit 17 - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low

pub fn usr_dout_hold(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 18>

Bit 18 - spi is hold at data out state the bit combined with spi_usr_hold_pol bit.

pub fn usr_din_hold(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 19>

Bit 19 - spi is hold at data in state the bit combined with spi_usr_hold_pol bit.

pub fn usr_dummy_hold(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 20>

Bit 20 - spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.

pub fn usr_addr_hold(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 21>

Bit 21 - spi is hold at address state the bit combined with spi_usr_hold_pol bit.

pub fn usr_cmd_hold(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 22>

Bit 22 - spi is hold at command state the bit combined with spi_usr_hold_pol bit.

pub fn usr_prep_hold(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 23>

Bit 23 - spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.

pub fn usr_miso_highpart(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 24>

Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.

pub fn usr_mosi_highpart(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 25>

Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.

pub fn usr_dummy_idle(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 26>

Bit 26 - spi clock is disable in dummy phase when the bit is enable.

pub fn usr_mosi(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 27>

Bit 27 - This bit enable the write-data phase of an operation.

pub fn usr_miso(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 28>

Bit 28 - This bit enable the read-data phase of an operation.

pub fn usr_dummy(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 29>

Bit 29 - This bit enable the dummy phase of an operation.

pub fn usr_addr(&mut self) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 30>

Bit 30 - This bit enable the address phase of an operation.

pub fn usr_command(
    &mut self
) -> BitWriterRaw<'_, u32, USER_SPEC, bool, BitM, 31>

Bit 31 - This bit enable the command phase of an operation.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<USER_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<USER_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<USER_SPEC>> for W

fn from(writer: W<USER_SPEC>) -> W

Converts to this type from the input type.