Struct esp32_hal::pac::spi0::user::R

pub struct R(_);

Register USER reader

Implementations

impl R

pub fn doutdin(&self) -> BitReaderRaw<bool>

Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable.

pub fn cs_hold(&self) -> BitReaderRaw<bool>

Bit 4 - spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.

pub fn cs_setup(&self) -> BitReaderRaw<bool>

Bit 5 - spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.

pub fn ck_i_edge(&self) -> BitReaderRaw<bool>

Bit 6 - In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.

pub fn ck_out_edge(&self) -> BitReaderRaw<bool>

Bit 7 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.

pub fn rd_byte_order(&self) -> BitReaderRaw<bool>

Bit 10 - In read-data (MISO) phase 1: big-endian 0: little_endian

pub fn wr_byte_order(&self) -> BitReaderRaw<bool>

Bit 11 - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian

pub fn fwrite_dual(&self) -> BitReaderRaw<bool>

Bit 12 - In the write operations read-data phase apply 2 signals

pub fn fwrite_quad(&self) -> BitReaderRaw<bool>

Bit 13 - In the write operations read-data phase apply 4 signals

pub fn fwrite_dio(&self) -> BitReaderRaw<bool>

Bit 14 - In the write operations address phase and read-data phase apply 2 signals.

pub fn fwrite_qio(&self) -> BitReaderRaw<bool>

Bit 15 - In the write operations address phase and read-data phase apply 4 signals.

pub fn sio(&self) -> BitReaderRaw<bool>

Bit 16 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.

pub fn usr_hold_pol(&self) -> BitReaderRaw<bool>

Bit 17 - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low

pub fn usr_dout_hold(&self) -> BitReaderRaw<bool>

Bit 18 - spi is hold at data out state the bit combined with spi_usr_hold_pol bit.

pub fn usr_din_hold(&self) -> BitReaderRaw<bool>

Bit 19 - spi is hold at data in state the bit combined with spi_usr_hold_pol bit.

pub fn usr_dummy_hold(&self) -> BitReaderRaw<bool>

Bit 20 - spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.

pub fn usr_addr_hold(&self) -> BitReaderRaw<bool>

Bit 21 - spi is hold at address state the bit combined with spi_usr_hold_pol bit.

pub fn usr_cmd_hold(&self) -> BitReaderRaw<bool>

Bit 22 - spi is hold at command state the bit combined with spi_usr_hold_pol bit.

pub fn usr_prep_hold(&self) -> BitReaderRaw<bool>

Bit 23 - spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.

pub fn usr_miso_highpart(&self) -> BitReaderRaw<bool>

Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.

pub fn usr_mosi_highpart(&self) -> BitReaderRaw<bool>

Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.

pub fn usr_dummy_idle(&self) -> BitReaderRaw<bool>

Bit 26 - spi clock is disable in dummy phase when the bit is enable.

pub fn usr_mosi(&self) -> BitReaderRaw<bool>

Bit 27 - This bit enable the write-data phase of an operation.

pub fn usr_miso(&self) -> BitReaderRaw<bool>

Bit 28 - This bit enable the read-data phase of an operation.

pub fn usr_dummy(&self) -> BitReaderRaw<bool>

Bit 29 - This bit enable the dummy phase of an operation.

pub fn usr_addr(&self) -> BitReaderRaw<bool>

Bit 30 - This bit enable the address phase of an operation.

pub fn usr_command(&self) -> BitReaderRaw<bool>

Bit 31 - This bit enable the command phase of an operation.

Methods from Deref<Target = R<USER_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<USER_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<USER_SPEC>> for R

fn from(reader: R<USER_SPEC>) -> R

Converts to this type from the input type.