Struct esp32_hal::pac::spi0::cache_sctrl::R

pub struct R(_);

Register CACHE_SCTRL reader

Implementations

impl R

pub fn usr_sram_dio(&self) -> BitReaderRaw<bool>

Bit 1 - For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable

pub fn usr_sram_qio(&self) -> BitReaderRaw<bool>

Bit 2 - For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable

pub fn usr_wr_sram_dummy(&self) -> BitReaderRaw<bool>

Bit 3 - For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.

pub fn usr_rd_sram_dummy(&self) -> BitReaderRaw<bool>

Bit 4 - For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.

pub fn cache_sram_usr_rcmd(&self) -> BitReaderRaw<bool>

Bit 5 - For SPI0 In the spi sram mode cache read sram for user define command.

pub fn sram_bytes_len(&self) -> FieldReaderRaw<u8, u8>

Bits 6:13 - For SPI0 In the sram mode it is the byte length of spi read sram data.

pub fn sram_dummy_cyclelen(&self) -> FieldReaderRaw<u8, u8>

Bits 14:21 - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).

pub fn sram_addr_bitlen(&self) -> FieldReaderRaw<u8, u8>

Bits 22:27 - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).

pub fn cache_sram_usr_wcmd(&self) -> BitReaderRaw<bool>

Bit 28 - For SPI0 In the spi sram mode cache write sram for user define command

Methods from Deref<Target = R<CACHE_SCTRL_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CACHE_SCTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<CACHE_SCTRL_SPEC>> for R

fn from(reader: R<CACHE_SCTRL_SPEC>) -> R

Converts to this type from the input type.