Struct esp32_hal::pac::sdmmc::idinten::R

pub struct R(_);

Register IDINTEN reader

Implementations

impl R

pub fn ti(&self) -> BitReaderRaw<bool>

Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled.

pub fn ri(&self) -> BitReaderRaw<bool>

Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled.

pub fn fbe(&self) -> BitReaderRaw<bool>

Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled.

pub fn du(&self) -> BitReaderRaw<bool>

Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled.

pub fn ces(&self) -> BitReaderRaw<bool>

Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary.

pub fn ni(&self) -> BitReaderRaw<bool>

Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0]: Transmit Interrupt; IDINTEN[1]: Receive Interrupt.

pub fn ai(&self) -> BitReaderRaw<bool>

Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2]: Fatal Bus Error Interrupt; IDINTEN[4]: DU Interrupt.

Methods from Deref<Target = R<IDINTEN_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<IDINTEN_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<IDINTEN_SPEC>> for R

fn from(reader: R<IDINTEN_SPEC>) -> R

Converts to this type from the input type.