Struct esp32_hal::pac::sdmmc::clk_edge_sel::W

pub struct W(_);

Register CLK_EDGE_SEL writer

Implementations

impl W

pub fn cclkin_edge_drv_sel(
    &mut self
) -> FieldWriterRaw<'_, u32, CLK_EDGE_SEL_SPEC, u8, u8, Unsafe, 3, 0>

Bits 0:2 - It’s used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270.

pub fn cclkin_edge_sam_sel(
    &mut self
) -> FieldWriterRaw<'_, u32, CLK_EDGE_SEL_SPEC, u8, u8, Unsafe, 3, 3>

Bits 3:5 - It’s used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270.

pub fn cclkin_edge_slf_sel(
    &mut self
) -> FieldWriterRaw<'_, u32, CLK_EDGE_SEL_SPEC, u8, u8, Unsafe, 3, 6>

Bits 6:8 - It’s used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270.

pub fn ccllkin_edge_h(
    &mut self
) -> FieldWriterRaw<'_, u32, CLK_EDGE_SEL_SPEC, u8, u8, Unsafe, 4, 9>

Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L.

pub fn ccllkin_edge_l(
    &mut self
) -> FieldWriterRaw<'_, u32, CLK_EDGE_SEL_SPEC, u8, u8, Unsafe, 4, 13>

Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H.

pub fn ccllkin_edge_n(
    &mut self
) -> FieldWriterRaw<'_, u32, CLK_EDGE_SEL_SPEC, u8, u8, Unsafe, 4, 17>

Bits 17:20 - The value should be equal to CCLKIN_EDGE_L.

pub fn esdio_mode(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_EDGE_SEL_SPEC, bool, BitM, 21>

Bit 21 - Enable esdio mode.

pub fn esd_mode(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_EDGE_SEL_SPEC, bool, BitM, 22>

Bit 22 - Enable esd mode.

pub fn cclk_en(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_EDGE_SEL_SPEC, bool, BitM, 23>

Bit 23 - Sdio clock enable

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CLK_EDGE_SEL_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CLK_EDGE_SEL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CLK_EDGE_SEL_SPEC>> for W

fn from(writer: W<CLK_EDGE_SEL_SPEC>) -> W

Converts to this type from the input type.