Struct esp32_hal::pac::sdmmc::clk_edge_sel::R

pub struct R(_);

Register CLK_EDGE_SEL reader

Implementations

impl R

pub fn cclkin_edge_drv_sel(&self) -> FieldReaderRaw<u8, u8>

Bits 0:2 - It’s used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270.

pub fn cclkin_edge_sam_sel(&self) -> FieldReaderRaw<u8, u8>

Bits 3:5 - It’s used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270.

pub fn cclkin_edge_slf_sel(&self) -> FieldReaderRaw<u8, u8>

Bits 6:8 - It’s used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270.

pub fn ccllkin_edge_h(&self) -> FieldReaderRaw<u8, u8>

Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L.

pub fn ccllkin_edge_l(&self) -> FieldReaderRaw<u8, u8>

Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H.

pub fn ccllkin_edge_n(&self) -> FieldReaderRaw<u8, u8>

Bits 17:20 - The value should be equal to CCLKIN_EDGE_L.

pub fn esdio_mode(&self) -> BitReaderRaw<bool>

Bit 21 - Enable esdio mode.

pub fn esd_mode(&self) -> BitReaderRaw<bool>

Bit 22 - Enable esd mode.

pub fn cclk_en(&self) -> BitReaderRaw<bool>

Bit 23 - Sdio clock enable

Methods from Deref<Target = R<CLK_EDGE_SEL_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CLK_EDGE_SEL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<CLK_EDGE_SEL_SPEC>> for R

fn from(reader: R<CLK_EDGE_SEL_SPEC>) -> R

Converts to this type from the input type.