Struct esp32_hal::pac::rtc_cntl::clk_conf::W

pub struct W(_);

Register CLK_CONF writer

Implementations

impl W

pub fn ck8m_div(
    &mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, CK8M_DIV_A, Safe, 2, 4>

Bits 4:5 - CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.

pub fn enb_ck8m(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 6>

Bit 6 - disable CK8M and CK8M_D256_OUT

pub fn enb_ck8m_div(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, ENB_CK8M_DIV_A, BitM, 7>

Bit 7 - 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256

pub fn dig_xtal32k_en(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 8>

Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)

pub fn dig_clk8m_d256_en(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 9>

Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)

pub fn dig_clk8m_en(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 10>

Bit 10 - enable CK8M for digital core (no relationship with RTC core)

pub fn ck8m_dfreq_force(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 11>

Bit 11

pub fn ck8m_div_sel(
    &mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, u8, Unsafe, 3, 12>

Bits 12:14 - divider = reg_ck8m_div_sel + 1

pub fn xtal_force_nogating(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 15>

Bit 15 - XTAL force no gating during sleep

pub fn ck8m_force_nogating(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 16>

Bit 16 - CK8M force no gating during sleep

pub fn ck8m_dfreq(
    &mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, u8, Unsafe, 8, 17>

Bits 17:24 - CK8M_DFREQ

pub fn ck8m_force_pd(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 25>

Bit 25 - CK8M force power down

pub fn ck8m_force_pu(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, bool, BitM, 26>

Bit 26 - CK8M force power up

pub fn soc_clk_sel(
    &mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, SOC_CLK_SEL_A, Safe, 2, 27>

Bits 27:28 - SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL

pub fn fast_clk_rtc_sel(
    &mut self
) -> BitWriterRaw<'_, u32, CLK_CONF_SPEC, FAST_CLK_RTC_SEL_A, BitM, 29>

Bit 29 - fast_clk_rtc sel. 0: XTAL div 4 1: CK8M

pub fn ana_clk_rtc_sel(
    &mut self
) -> FieldWriterRaw<'_, u32, CLK_CONF_SPEC, u8, ANA_CLK_RTC_SEL_A, Unsafe, 2, 30>

Bits 30:31 - slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CLK_CONF_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CLK_CONF_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CLK_CONF_SPEC>> for W

fn from(writer: W<CLK_CONF_SPEC>) -> W

Converts to this type from the input type.