pub struct R(_);
Expand description
Register CLK_CONF
reader
Implementations§
§impl R
impl R
pub fn ck8m_div(&self) -> FieldReaderRaw<u8, CK8M_DIV_A>
pub fn ck8m_div(&self) -> FieldReaderRaw<u8, CK8M_DIV_A>
Bits 4:5 - CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.
pub fn enb_ck8m_div(&self) -> BitReaderRaw<ENB_CK8M_DIV_A>
pub fn enb_ck8m_div(&self) -> BitReaderRaw<ENB_CK8M_DIV_A>
Bit 7 - 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256
pub fn dig_xtal32k_en(&self) -> BitReaderRaw<bool>
pub fn dig_xtal32k_en(&self) -> BitReaderRaw<bool>
Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)
pub fn dig_clk8m_d256_en(&self) -> BitReaderRaw<bool>
pub fn dig_clk8m_d256_en(&self) -> BitReaderRaw<bool>
Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)
pub fn dig_clk8m_en(&self) -> BitReaderRaw<bool>
pub fn dig_clk8m_en(&self) -> BitReaderRaw<bool>
Bit 10 - enable CK8M for digital core (no relationship with RTC core)
pub fn ck8m_dfreq_force(&self) -> BitReaderRaw<bool>
pub fn ck8m_dfreq_force(&self) -> BitReaderRaw<bool>
Bit 11
pub fn ck8m_div_sel(&self) -> FieldReaderRaw<u8, u8>
pub fn ck8m_div_sel(&self) -> FieldReaderRaw<u8, u8>
Bits 12:14 - divider = reg_ck8m_div_sel + 1
pub fn xtal_force_nogating(&self) -> BitReaderRaw<bool>
pub fn xtal_force_nogating(&self) -> BitReaderRaw<bool>
Bit 15 - XTAL force no gating during sleep
pub fn ck8m_force_nogating(&self) -> BitReaderRaw<bool>
pub fn ck8m_force_nogating(&self) -> BitReaderRaw<bool>
Bit 16 - CK8M force no gating during sleep
pub fn ck8m_dfreq(&self) -> FieldReaderRaw<u8, u8>
pub fn ck8m_dfreq(&self) -> FieldReaderRaw<u8, u8>
Bits 17:24 - CK8M_DFREQ
pub fn ck8m_force_pd(&self) -> BitReaderRaw<bool>
pub fn ck8m_force_pd(&self) -> BitReaderRaw<bool>
Bit 25 - CK8M force power down
pub fn ck8m_force_pu(&self) -> BitReaderRaw<bool>
pub fn ck8m_force_pu(&self) -> BitReaderRaw<bool>
Bit 26 - CK8M force power up
pub fn soc_clk_sel(&self) -> FieldReaderRaw<u8, SOC_CLK_SEL_A>
pub fn soc_clk_sel(&self) -> FieldReaderRaw<u8, SOC_CLK_SEL_A>
Bits 27:28 - SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL
pub fn fast_clk_rtc_sel(&self) -> BitReaderRaw<FAST_CLK_RTC_SEL_A>
pub fn fast_clk_rtc_sel(&self) -> BitReaderRaw<FAST_CLK_RTC_SEL_A>
Bit 29 - fast_clk_rtc sel. 0: XTAL div 4 1: CK8M
pub fn ana_clk_rtc_sel(&self) -> FieldReaderRaw<u8, ANA_CLK_RTC_SEL_A>
pub fn ana_clk_rtc_sel(&self) -> FieldReaderRaw<u8, ANA_CLK_RTC_SEL_A>
Bits 30:31 - slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT
Methods from Deref<Target = R<CLK_CONF_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.