pub struct W(_);
Expand description
Register U3_CONF0
writer
Implementations§
§impl W
impl W
pub fn filter_thres_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u16, u16, Unsafe, 10, 0>
pub fn filter_thres_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u16, u16, Unsafe, 10, 0>
Bits 0:9 - This register is used to filter pluse whose width is smaller than this value for unit3.
pub fn filter_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 10>
pub fn filter_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 10>
Bit 10 - This is the enable bit for filtering input signals for unit3.
pub fn thr_zero_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 11>
pub fn thr_zero_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 11>
Bit 11 - This is the enable bit for comparing unit3’s count with 0 value.
pub fn thr_h_lim_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 12>
pub fn thr_h_lim_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 12>
Bit 12 - This is the enable bit for comparing unit3’s count with thr_h_lim value.
pub fn thr_l_lim_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 13>
pub fn thr_l_lim_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 13>
Bit 13 - This is the enable bit for comparing unit3’s count with thr_l_lim value.
pub fn thr_thres0_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 14>
pub fn thr_thres0_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 14>
Bit 14 - This is the enable bit for comparing unit3’s count with thres0 value.
pub fn thr_thres1_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 15>
pub fn thr_thres1_en_u3(
&mut self
) -> BitWriterRaw<'_, u32, U3_CONF0_SPEC, bool, BitM, 15>
Bit 15 - This is the enable bit for comparing unit3’s count with thres1 value .
pub fn ch0_neg_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 16>
pub fn ch0_neg_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 16>
Bits 16:17 - This register is used to control the mode of channel0’s input negedge signal for unit3. 2’d1: increase at the negedge of input signal 2’d2:decrease at the negedge of input signal others:forbidden
pub fn ch0_pos_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 18>
pub fn ch0_pos_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 18>
Bits 18:19 - This register is used to control the mode of channel0’s input posedge signal for unit3. 2’d1: increase at the posedge of input signal 2’d2:decrease at the posedge of input signal others:forbidden
pub fn ch0_hctrl_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 20>
pub fn ch0_hctrl_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 20>
Bits 20:21 - This register is used to control the mode of channel0’s high control signal for unit3. 2’d0:increase when control signal is low 2’d1: decrease when control signal is high others:forbidden
pub fn ch0_lctrl_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 22>
pub fn ch0_lctrl_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 22>
Bits 22:23 - This register is used to control the mode of channel0’s low control signal for unit3. 2’d0:increase when control signal is low 2’d1: decrease when control signal is high others:forbidden
pub fn ch1_neg_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 24>
pub fn ch1_neg_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 24>
Bits 24:25 - This register is used to control the mode of channel1’s input negedge signal for unit3. 2’d1: increase at the negedge of input signal 2’d2:decrease at the negedge of input signal others:forbidden
pub fn ch1_pos_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 26>
pub fn ch1_pos_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 26>
Bits 26:27 - This register is used to control the mode of channel1’s input posedge signal for unit3. 2’d1: increase at the posedge of input signal 2’d2:decrease at the posedge of input signal others:forbidden
pub fn ch1_hctrl_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 28>
pub fn ch1_hctrl_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 28>
Bits 28:29 - This register is used to control the mode of channel1’s high control signal for unit3. 2’d0:increase when control signal is low 2’d1: decrease when control signal is high others:forbidden
pub fn ch1_lctrl_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 30>
pub fn ch1_lctrl_mode_u3(
&mut self
) -> FieldWriterRaw<'_, u32, U3_CONF0_SPEC, u8, u8, Unsafe, 2, 30>
Bits 30:31 - This register is used to control the mode of channel1’s low control signal for unit3. 2’d0:increase when control signal is low 2’d1: decrease when control signal is high others:forbidden
Methods from Deref<Target = W<U3_CONF0_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.