Struct esp32_hal::pac::ledc::int_ena::W

pub struct W(_);

Register INT_ENA writer

Implementations

impl W

pub fn hstimer0_ovf_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 0>

Bit 0 - The interrupt enable bit for high speed channel0 counter overflow interrupt.

pub fn hstimer1_ovf_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 1>

Bit 1 - The interrupt enable bit for high speed channel1 counter overflow interrupt.

pub fn hstimer2_ovf_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 2>

Bit 2 - The interrupt enable bit for high speed channel2 counter overflow interrupt.

pub fn hstimer3_ovf_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 3>

Bit 3 - The interrupt enable bit for high speed channel3 counter overflow interrupt.

pub fn lstimer0_ovf_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 4>

Bit 4 - The interrupt enable bit for low speed channel0 counter overflow interrupt.

pub fn lstimer1_ovf_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 5>

Bit 5 - The interrupt enable bit for low speed channel1 counter overflow interrupt.

pub fn lstimer2_ovf_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 6>

Bit 6 - The interrupt enable bit for low speed channel2 counter overflow interrupt.

pub fn lstimer3_ovf_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 7>

Bit 7 - The interrupt enable bit for low speed channel3 counter overflow interrupt.

pub fn duty_chng_end_hsch0_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 8>

Bit 8 - The interrupt enable bit for high speed channel 0 duty change done interrupt.

pub fn duty_chng_end_hsch1_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 9>

Bit 9 - The interrupt enable bit for high speed channel 1 duty change done interrupt.

pub fn duty_chng_end_hsch2_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 10>

Bit 10 - The interrupt enable bit for high speed channel 2 duty change done interrupt.

pub fn duty_chng_end_hsch3_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 11>

Bit 11 - The interrupt enable bit for high speed channel 3 duty change done interrupt.

pub fn duty_chng_end_hsch4_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 12>

Bit 12 - The interrupt enable bit for high speed channel 4 duty change done interrupt.

pub fn duty_chng_end_hsch5_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 13>

Bit 13 - The interrupt enable bit for high speed channel 5 duty change done interrupt.

pub fn duty_chng_end_hsch6_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 14>

Bit 14 - The interrupt enable bit for high speed channel 6 duty change done interrupt.

pub fn duty_chng_end_hsch7_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 15>

Bit 15 - The interrupt enable bit for high speed channel 7 duty change done interrupt.

pub fn duty_chng_end_lsch0_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 16>

Bit 16 - The interrupt enable bit for low speed channel 0 duty change done interrupt.

pub fn duty_chng_end_lsch1_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 17>

Bit 17 - The interrupt enable bit for low speed channel 1 duty change done interrupt.

pub fn duty_chng_end_lsch2_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 18>

Bit 18 - The interrupt enable bit for low speed channel 2 duty change done interrupt.

pub fn duty_chng_end_lsch3_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 19>

Bit 19 - The interrupt enable bit for low speed channel 3 duty change done interrupt.

pub fn duty_chng_end_lsch4_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 20>

Bit 20 - The interrupt enable bit for low speed channel 4 duty change done interrupt.

pub fn duty_chng_end_lsch5_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 21>

Bit 21 - The interrupt enable bit for low speed channel 5 duty change done interrupt.

pub fn duty_chng_end_lsch6_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 22>

Bit 22 - The interrupt enable bit for low speed channel 6 duty change done interrupt.

pub fn duty_chng_end_lsch7_int_ena(
    &mut self
) -> BitWriterRaw<'_, u32, INT_ENA_SPEC, bool, BitM, 23>

Bit 23 - The interrupt enable bit for low speed channel 7 duty change done interrupt.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<INT_ENA_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<INT_ENA_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<INT_ENA_SPEC>> for W

fn from(writer: W<INT_ENA_SPEC>) -> W

Converts to this type from the input type.