Struct esp32_hal::pac::spi0::ctrl2::W

pub struct W(_);

Register CTRL2 writer

Implementations

impl W

pub fn setup_time(
    &mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 4, 0>

Bits 0:3 - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit.

pub fn hold_time(
    &mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 4, 4>

Bits 4:7 - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.

pub fn ck_out_low_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 4, 8>

Bits 8:11 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.

pub fn ck_out_high_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 4, 12>

Bits 12:15 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.

pub fn miso_delay_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 2, 16>

Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

pub fn miso_delay_num(
    &mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 3, 18>

Bits 18:20 - MISO signals are delayed by system clock cycles

pub fn mosi_delay_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 2, 21>

Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

pub fn mosi_delay_num(
    &mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 3, 23>

Bits 23:25 - MOSI signals are delayed by system clock cycles

pub fn cs_delay_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 2, 26>

Bits 26:27 - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

pub fn cs_delay_num(
    &mut self
) -> FieldWriterRaw<'_, u32, CTRL2_SPEC, u8, u8, Unsafe, 4, 28>

Bits 28:31 - spi_cs signal is delayed by system clock cycles

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CTRL2_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CTRL2_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CTRL2_SPEC>> for W

fn from(writer: W<CTRL2_SPEC>) -> W

Converts to this type from the input type.