pub struct W(_);
Expand description
Register IDINTEN
writer
Implementations§
§impl W
impl W
pub fn ti(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 0>
pub fn ti(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 0>
Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled.
pub fn ri(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 1>
pub fn ri(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 1>
Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled.
pub fn fbe(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 2>
pub fn fbe(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 2>
Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled.
pub fn du(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 4>
pub fn du(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 4>
Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled.
pub fn ces(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 5>
pub fn ces(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 5>
Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary.
pub fn ni(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 8>
pub fn ni(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 8>
Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0]: Transmit Interrupt; IDINTEN[1]: Receive Interrupt.
pub fn ai(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 9>
pub fn ai(&mut self) -> BitWriterRaw<'_, u32, IDINTEN_SPEC, bool, BitM, 9>
Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2]: Fatal Bus Error Interrupt; IDINTEN[4]: DU Interrupt.
Methods from Deref<Target = W<IDINTEN_SPEC>>§
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.