Struct esp32_hal::pac::i2c0::sr::R

pub struct R(_);

Expand description

Register SR reader

Implementations§

§

impl R

pub fn ack_rec(&self) -> BitReaderRaw<bool>

Bit 0 - This register stores the value of ACK bit.

pub fn slave_rw(&self) -> BitReaderRaw<bool>

Bit 1 - when in slave mode 1: master read slave 0: master write slave.

pub fn time_out(&self) -> BitReaderRaw<bool>

Bit 2 - when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.

pub fn arb_lost(&self) -> BitReaderRaw<bool>

Bit 3 - when I2C lost control of SDA line this register changes to high level.

pub fn bus_busy(&self) -> BitReaderRaw<bool>

Bit 4 - 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.

pub fn slave_addressed(&self) -> BitReaderRaw<bool>

Bit 5 - when configured as i2c slave and the address send by master is equal to slave’s address then this bit will be high level.

pub fn byte_trans(&self) -> BitReaderRaw<bool>

Bit 6 - This register changes to high level when one byte is transferred.

pub fn rxfifo_cnt(&self) -> FieldReaderRaw<u8, u8>

Bits 8:13 - This register represent the amount of data need to send.

pub fn txfifo_cnt(&self) -> FieldReaderRaw<u8, u8>

Bits 18:23 - This register stores the amount of received data in ram.

pub fn scl_main_state_last(&self) -> FieldReaderRaw<u8, u8>

Bits 24:26 - This register stores the value of state machine for i2c module. 3’h0: SCL_MAIN_IDLE 3’h1: SCL_ADDRESS_SHIFT 3’h2: SCL_ACK_ADDRESS 3’h3: SCL_RX_DATA 3’h4 SCL_TX_DATA 3’h5:SCL_SEND_ACK 3’h6:SCL_WAIT_ACK

pub fn scl_state_last(&self) -> FieldReaderRaw<u8, u8>

Bits 28:30 - This register stores the value of state machine to produce SCL. 3’h0: SCL_IDLE 3’h1:SCL_START 3’h2:SCL_LOW_EDGE 3’h3: SCL_LOW 3’h4:SCL_HIGH_EDGE 3’h5:SCL_HIGH 3’h6:SCL_STOP