Enum esp32_hal::xtensa_lx_rt::exception::ExceptionCause

#[repr(C)]
pub enum ExceptionCause {
    Illegal = 0,
    Syscall = 1,
    InstrError = 2,
    LoadStoreError = 3,
    LevelOneInterrupt = 4,
    Alloca = 5,
    DivideByZero = 6,
    NextPCValueIllegal = 7,
    Privileged = 8,
    Unaligned = 9,
    ExternalRegisterPrivilegeError = 10,
    ExclusiveError = 11,
    InstrDataError = 12,
    LoadStoreDataError = 13,
    InstrAddrError = 14,
    LoadStoreAddrError = 15,
    ItlbMiss = 16,
    ItlbMultiHit = 17,
    InstrRing = 18,
    Reserved19 = 19,
    InstrProhibited = 20,
    Reserved21 = 21,
    Reserved22 = 22,
    Reserved23 = 23,
    DtlbMiss = 24,
    DtlbMultiHit = 25,
    LoadStoreRing = 26,
    Reserved27 = 27,
    LoadProhibited = 28,
    StoreProhibited = 29,
    Reserved30 = 30,
    Reserved31 = 31,
    Cp0Disabled = 32,
    Cp1Disabled = 33,
    Cp2Disabled = 34,
    Cp3Disabled = 35,
    Cp4Disabled = 36,
    Cp5Disabled = 37,
    Cp6Disabled = 38,
    Cp7Disabled = 39,
    None = 255,
}

EXCCAUSE register values

General Exception Causes. (Values of EXCCAUSE special register set by general exceptions, which vector to the user, kernel, or double-exception vectors).

Variants

Illegal = 0

Illegal Instruction

Syscall = 1

System Call (Syscall Instruction)

InstrError = 2

Instruction Fetch Error

LoadStoreError = 3

Load Store Error

LevelOneInterrupt = 4

Level 1 Interrupt

Alloca = 5

Stack Extension Assist (movsp Instruction) For Alloca

DivideByZero = 6

Integer Divide By Zero

NextPCValueIllegal = 7

Use Of Failed Speculative Access (Not Implemented)

Privileged = 8

Privileged Instruction

Unaligned = 9

Unaligned Load Or Store

ExternalRegisterPrivilegeError = 10

Reserved

ExclusiveError = 11

Reserved

InstrDataError = 12

Pif Data Error On Instruction Fetch (Rb-200x And Later)

LoadStoreDataError = 13

Pif Data Error On Load Or Store (Rb-200x And Later)

InstrAddrError = 14

Pif Address Error On Instruction Fetch (Rb-200x And Later)

LoadStoreAddrError = 15

Pif Address Error On Load Or Store (Rb-200x And Later)

ItlbMiss = 16

Itlb Miss (No Itlb Entry Matches, Hw Refill Also Missed)

ItlbMultiHit = 17

Itlb Multihit (Multiple Itlb Entries Match)

InstrRing = 18

Ring Privilege Violation On Instruction Fetch

Reserved19 = 19

Size Restriction On Ifetch (Not Implemented)

InstrProhibited = 20

Cache Attribute Does Not Allow Instruction Fetch

Reserved21 = 21

Reserved

Reserved22 = 22

Reserved

Reserved23 = 23

Reserved

DtlbMiss = 24

Dtlb Miss (No Dtlb Entry Matches, Hw Refill Also Missed)

DtlbMultiHit = 25

Dtlb Multihit (Multiple Dtlb Entries Match)

LoadStoreRing = 26

Ring Privilege Violation On Load Or Store

Reserved27 = 27

Size Restriction On Load/Store (Not Implemented)

LoadProhibited = 28

Cache Attribute Does Not Allow Load

StoreProhibited = 29

Cache Attribute Does Not Allow Store

Reserved30 = 30

Reserved

Reserved31 = 31

Reserved

Cp0Disabled = 32

Access To Coprocessor 0 When Disabled

Cp1Disabled = 33

Access To Coprocessor 1 When Disabled

Cp2Disabled = 34

Access To Coprocessor 2 When Disabled

Cp3Disabled = 35

Access To Coprocessor 3 When Disabled

Cp4Disabled = 36

Access To Coprocessor 4 When Disabled

Cp5Disabled = 37

Access To Coprocessor 5 When Disabled

Cp6Disabled = 38

Access To Coprocessor 6 When Disabled

Cp7Disabled = 39

Access To Coprocessor 7 When Disabled

None = 255

Trait Implementations

impl Debug for ExceptionCause

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.