pub enum DirectBindableCpuInterrupt {
Interrupt0 = 1,
Interrupt1 = 2,
Interrupt2 = 5,
Interrupt3 = 6,
Interrupt4 = 8,
Interrupt5 = 9,
Interrupt6 = 10,
Interrupt7 = 11,
Interrupt8 = 12,
Interrupt9 = 13,
Interrupt10 = 14,
Interrupt11 = 15,
}unstable only.Expand description
Enumeration of CPU interrupts available for direct binding.
§Stability
This API is marked as unstable and is only available when the unstable
crate feature is enabled. This comes with no stability guarantees, and could be changed
or removed at any time.
Variants§
Interrupt0 = 1
Direct bindable CPU interrupt number 0.
Corresponds to CPU interrupt 1.
Interrupt1 = 2
Direct bindable CPU interrupt number 1.
Corresponds to CPU interrupt 2.
Interrupt2 = 5
Direct bindable CPU interrupt number 2.
Corresponds to CPU interrupt 5.
Interrupt3 = 6
Direct bindable CPU interrupt number 3.
Corresponds to CPU interrupt 6.
Interrupt4 = 8
Direct bindable CPU interrupt number 4.
Corresponds to CPU interrupt 8.
Interrupt5 = 9
Direct bindable CPU interrupt number 5.
Corresponds to CPU interrupt 9.
Interrupt6 = 10
Direct bindable CPU interrupt number 6.
Corresponds to CPU interrupt 10.
Interrupt7 = 11
Direct bindable CPU interrupt number 7.
Corresponds to CPU interrupt 11.
Interrupt8 = 12
Direct bindable CPU interrupt number 8.
Corresponds to CPU interrupt 12.
Interrupt9 = 13
Direct bindable CPU interrupt number 9.
Corresponds to CPU interrupt 13.
Interrupt10 = 14
Direct bindable CPU interrupt number 10.
Corresponds to CPU interrupt 14.
Interrupt11 = 15
Direct bindable CPU interrupt number 11.
Corresponds to CPU interrupt 15.
Trait Implementations§
Source§impl Clone for DirectBindableCpuInterrupt
impl Clone for DirectBindableCpuInterrupt
Source§fn clone(&self) -> DirectBindableCpuInterrupt
fn clone(&self) -> DirectBindableCpuInterrupt
1.0.0 (const: unstable) · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more