pub struct SPI1 { /* private fields */ }Expand description
Represents a virtual peripheral with no associated hardware.
This struct is generated by the create_peripheral! macro when the peripheral
is defined as virtual.
Implementations§
Methods from Deref<Target = RegisterBlock>§
Sourcepub fn ctrl1(&self) -> &Reg<CTRL1_SPEC>
pub fn ctrl1(&self) -> &Reg<CTRL1_SPEC>
0x0c - SPI1 control1 register.
Sourcepub fn ctrl2(&self) -> &Reg<CTRL2_SPEC>
pub fn ctrl2(&self) -> &Reg<CTRL2_SPEC>
0x10 - SPI1 control2 register.
Sourcepub fn clock(&self) -> &Reg<CLOCK_SPEC>
pub fn clock(&self) -> &Reg<CLOCK_SPEC>
0x14 - SPI1 clock division control register.
Sourcepub fn user1(&self) -> &Reg<USER1_SPEC>
pub fn user1(&self) -> &Reg<USER1_SPEC>
0x1c - SPI1 user1 register.
Sourcepub fn user2(&self) -> &Reg<USER2_SPEC>
pub fn user2(&self) -> &Reg<USER2_SPEC>
0x20 - SPI1 user2 register.
Sourcepub fn mosi_dlen(&self) -> &Reg<MOSI_DLEN_SPEC>
pub fn mosi_dlen(&self) -> &Reg<MOSI_DLEN_SPEC>
0x24 - SPI1 send data bit length control register.
Sourcepub fn miso_dlen(&self) -> &Reg<MISO_DLEN_SPEC>
pub fn miso_dlen(&self) -> &Reg<MISO_DLEN_SPEC>
0x28 - SPI1 receive data bit length control register.
Sourcepub fn rd_status(&self) -> &Reg<RD_STATUS_SPEC>
pub fn rd_status(&self) -> &Reg<RD_STATUS_SPEC>
0x2c - SPI1 status register.
Sourcepub fn tx_crc(&self) -> &Reg<TX_CRC_SPEC>
pub fn tx_crc(&self) -> &Reg<TX_CRC_SPEC>
0x38 - SPI1 TX CRC data register.
Sourcepub fn cache_fctrl(&self) -> &Reg<CACHE_FCTRL_SPEC>
pub fn cache_fctrl(&self) -> &Reg<CACHE_FCTRL_SPEC>
0x3c - SPI1 bit mode control register.
Sourcepub fn w_iter(&self) -> impl Iterator<Item = &Reg<W_SPEC>>
pub fn w_iter(&self) -> impl Iterator<Item = &Reg<W_SPEC>>
Iterator for array of: 0x58..0x98 - SPI1 memory data buffer%s
Sourcepub fn flash_waiti_ctrl(&self) -> &Reg<FLASH_WAITI_CTRL_SPEC>
pub fn flash_waiti_ctrl(&self) -> &Reg<FLASH_WAITI_CTRL_SPEC>
0x98 - SPI1 wait idle control register
Sourcepub fn flash_sus_ctrl(&self) -> &Reg<FLASH_SUS_CTRL_SPEC>
pub fn flash_sus_ctrl(&self) -> &Reg<FLASH_SUS_CTRL_SPEC>
0x9c - SPI1 flash suspend control register
Sourcepub fn flash_sus_cmd(&self) -> &Reg<FLASH_SUS_CMD_SPEC>
pub fn flash_sus_cmd(&self) -> &Reg<FLASH_SUS_CMD_SPEC>
0xa0 - SPI1 flash suspend command register
Sourcepub fn sus_status(&self) -> &Reg<SUS_STATUS_SPEC>
pub fn sus_status(&self) -> &Reg<SUS_STATUS_SPEC>
0xa4 - SPI1 flash suspend status register
Sourcepub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>
pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>
0xc0 - SPI1 interrupt enable register
Sourcepub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>
pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>
0xc4 - SPI1 interrupt clear register
Sourcepub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>
pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>
0xc8 - SPI1 interrupt raw register
Sourcepub fn int_st(&self) -> &Reg<INT_ST_SPEC>
pub fn int_st(&self) -> &Reg<INT_ST_SPEC>
0xcc - SPI1 interrupt status register
Sourcepub fn timing_cali(&self) -> &Reg<TIMING_CALI_SPEC>
pub fn timing_cali(&self) -> &Reg<TIMING_CALI_SPEC>
0x180 - SPI1 timing control register
Sourcepub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>
pub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>
0x200 - SPI1 clk_gate register