Struct SPI0

pub struct SPI0 { /* private fields */ }

Represents a virtual peripheral with no associated hardware.

This struct is generated by the create_peripheral! macro when the peripheral is defined as virtual.

Implementations

impl SPI0

pub unsafe fn steal() -> Self

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

impl SPI0

pub const PTR: *const <SPI0 as Deref>::Target = {0x60002000 as *const <esp32c6::SPI0 as core::ops::Deref>::Target}

Pointer to the register block

pub const fn ptr() -> *const <SPI0 as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn cmd(&self) -> &Reg<CMD_SPEC>

0x00 - SPI0 FSM status register

pub fn ctrl(&self) -> &Reg<CTRL_SPEC>

0x08 - SPI0 control register.

pub fn ctrl1(&self) -> &Reg<CTRL1_SPEC>

0x0c - SPI0 control1 register.

pub fn ctrl2(&self) -> &Reg<CTRL2_SPEC>

0x10 - SPI0 control2 register.

pub fn clock(&self) -> &Reg<CLOCK_SPEC>

0x14 - SPI clock division control register.

pub fn user(&self) -> &Reg<USER_SPEC>

0x18 - SPI0 user register.

pub fn user1(&self) -> &Reg<USER1_SPEC>

0x1c - SPI0 user1 register.

pub fn user2(&self) -> &Reg<USER2_SPEC>

0x20 - SPI0 user2 register.

pub fn rd_status(&self) -> &Reg<RD_STATUS_SPEC>

0x2c - SPI0 read control register.

pub fn misc(&self) -> &Reg<MISC_SPEC>

0x34 - SPI0 misc register

pub fn cache_fctrl(&self) -> &Reg<CACHE_FCTRL_SPEC>

0x3c - SPI0 bit mode control register.

pub fn cache_sctrl(&self) -> &Reg<CACHE_SCTRL_SPEC>

0x40 - SPI0 external RAM control register

pub fn sram_cmd(&self) -> &Reg<SRAM_CMD_SPEC>

0x44 - SPI0 external RAM mode control register

pub fn sram_drd_cmd(&self) -> &Reg<SRAM_DRD_CMD_SPEC>

0x48 - SPI0 external RAM DDR read command control register

pub fn sram_dwr_cmd(&self) -> &Reg<SRAM_DWR_CMD_SPEC>

0x4c - SPI0 external RAM DDR write command control register

pub fn sram_clk(&self) -> &Reg<SRAM_CLK_SPEC>

0x50 - SPI0 external RAM clock control register

pub fn fsm(&self) -> &Reg<FSM_SPEC>

0x54 - SPI0 FSM status register

pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>

0xc0 - SPI0 interrupt enable register

pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>

0xc4 - SPI0 interrupt clear register

pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>

0xc8 - SPI0 interrupt raw register

pub fn int_st(&self) -> &Reg<INT_ST_SPEC>

0xcc - SPI0 interrupt status register

pub fn ddr(&self) -> &Reg<DDR_SPEC>

0xd4 - SPI0 flash DDR mode control register

pub fn spi_smem_ddr(&self) -> &Reg<SPI_SMEM_DDR_SPEC>

0xd8 - SPI0 external RAM DDR mode control register

pub fn spi_fmem_pms_attr(&self, n: usize) -> &Reg<SPI_FMEM_PMS_ATTR_SPEC>

0x100..0x110 - MSPI flash ACE section %s attribute register

pub fn spi_fmem_pms_attr_iter( &self, ) -> impl Iterator<Item = &Reg<SPI_FMEM_PMS_ATTR_SPEC>>

Iterator for array of: 0x100..0x110 - MSPI flash ACE section %s attribute register

pub fn spi_fmem_pms0_attr(&self) -> &Reg<SPI_FMEM_PMS_ATTR_SPEC>

0x100 - MSPI flash ACE section 0 attribute register

pub fn spi_fmem_pms1_attr(&self) -> &Reg<SPI_FMEM_PMS_ATTR_SPEC>

0x104 - MSPI flash ACE section 1 attribute register

pub fn spi_fmem_pms2_attr(&self) -> &Reg<SPI_FMEM_PMS_ATTR_SPEC>

0x108 - MSPI flash ACE section 2 attribute register

pub fn spi_fmem_pms3_attr(&self) -> &Reg<SPI_FMEM_PMS_ATTR_SPEC>

0x10c - MSPI flash ACE section 3 attribute register

pub fn spi_fmem_pms_addr(&self, n: usize) -> &Reg<SPI_FMEM_PMS_ADDR_SPEC>

0x110..0x120 - SPI1 flash ACE section %s start address register

pub fn spi_fmem_pms_addr_iter( &self, ) -> impl Iterator<Item = &Reg<SPI_FMEM_PMS_ADDR_SPEC>>

Iterator for array of: 0x110..0x120 - SPI1 flash ACE section %s start address register

pub fn spi_fmem_pms0_addr(&self) -> &Reg<SPI_FMEM_PMS_ADDR_SPEC>

0x110 - SPI1 flash ACE section 0 start address register

pub fn spi_fmem_pms1_addr(&self) -> &Reg<SPI_FMEM_PMS_ADDR_SPEC>

0x114 - SPI1 flash ACE section 1 start address register

pub fn spi_fmem_pms2_addr(&self) -> &Reg<SPI_FMEM_PMS_ADDR_SPEC>

0x118 - SPI1 flash ACE section 2 start address register

pub fn spi_fmem_pms3_addr(&self) -> &Reg<SPI_FMEM_PMS_ADDR_SPEC>

0x11c - SPI1 flash ACE section 3 start address register

pub fn spi_fmem_pms_size(&self, n: usize) -> &Reg<SPI_FMEM_PMS_SIZE_SPEC>

0x120..0x130 - SPI1 flash ACE section %s start address register

pub fn spi_fmem_pms_size_iter( &self, ) -> impl Iterator<Item = &Reg<SPI_FMEM_PMS_SIZE_SPEC>>

Iterator for array of: 0x120..0x130 - SPI1 flash ACE section %s start address register

pub fn spi_fmem_pms0_size(&self) -> &Reg<SPI_FMEM_PMS_SIZE_SPEC>

0x120 - SPI1 flash ACE section 0 start address register

pub fn spi_fmem_pms1_size(&self) -> &Reg<SPI_FMEM_PMS_SIZE_SPEC>

0x124 - SPI1 flash ACE section 1 start address register

pub fn spi_fmem_pms2_size(&self) -> &Reg<SPI_FMEM_PMS_SIZE_SPEC>

0x128 - SPI1 flash ACE section 2 start address register

pub fn spi_fmem_pms3_size(&self) -> &Reg<SPI_FMEM_PMS_SIZE_SPEC>

0x12c - SPI1 flash ACE section 3 start address register

pub fn spi_smem_pms_attr(&self, n: usize) -> &Reg<SPI_SMEM_PMS_ATTR_SPEC>

0x130..0x140 - SPI1 flash ACE section %s start address register

pub fn spi_smem_pms_attr_iter( &self, ) -> impl Iterator<Item = &Reg<SPI_SMEM_PMS_ATTR_SPEC>>

Iterator for array of: 0x130..0x140 - SPI1 flash ACE section %s start address register

pub fn spi_smem_pms0_attr(&self) -> &Reg<SPI_SMEM_PMS_ATTR_SPEC>

0x130 - SPI1 flash ACE section 0 start address register

pub fn spi_smem_pms1_attr(&self) -> &Reg<SPI_SMEM_PMS_ATTR_SPEC>

0x134 - SPI1 flash ACE section 1 start address register

pub fn spi_smem_pms2_attr(&self) -> &Reg<SPI_SMEM_PMS_ATTR_SPEC>

0x138 - SPI1 flash ACE section 2 start address register

pub fn spi_smem_pms3_attr(&self) -> &Reg<SPI_SMEM_PMS_ATTR_SPEC>

0x13c - SPI1 flash ACE section 3 start address register

pub fn spi_smem_pms_addr(&self, n: usize) -> &Reg<SPI_SMEM_PMS_ADDR_SPEC>

0x140..0x150 - SPI1 external RAM ACE section %s start address register

pub fn spi_smem_pms_addr_iter( &self, ) -> impl Iterator<Item = &Reg<SPI_SMEM_PMS_ADDR_SPEC>>

Iterator for array of: 0x140..0x150 - SPI1 external RAM ACE section %s start address register

pub fn spi_smem_pms0_addr(&self) -> &Reg<SPI_SMEM_PMS_ADDR_SPEC>

0x140 - SPI1 external RAM ACE section 0 start address register

pub fn spi_smem_pms1_addr(&self) -> &Reg<SPI_SMEM_PMS_ADDR_SPEC>

0x144 - SPI1 external RAM ACE section 1 start address register

pub fn spi_smem_pms2_addr(&self) -> &Reg<SPI_SMEM_PMS_ADDR_SPEC>

0x148 - SPI1 external RAM ACE section 2 start address register

pub fn spi_smem_pms3_addr(&self) -> &Reg<SPI_SMEM_PMS_ADDR_SPEC>

0x14c - SPI1 external RAM ACE section 3 start address register

pub fn spi_smem_pms_size(&self, n: usize) -> &Reg<SPI_SMEM_PMS_SIZE_SPEC>

0x150..0x160 - SPI1 external RAM ACE section %s start address register

pub fn spi_smem_pms_size_iter( &self, ) -> impl Iterator<Item = &Reg<SPI_SMEM_PMS_SIZE_SPEC>>

Iterator for array of: 0x150..0x160 - SPI1 external RAM ACE section %s start address register

pub fn spi_smem_pms0_size(&self) -> &Reg<SPI_SMEM_PMS_SIZE_SPEC>

0x150 - SPI1 external RAM ACE section 0 start address register

pub fn spi_smem_pms1_size(&self) -> &Reg<SPI_SMEM_PMS_SIZE_SPEC>

0x154 - SPI1 external RAM ACE section 1 start address register

pub fn spi_smem_pms2_size(&self) -> &Reg<SPI_SMEM_PMS_SIZE_SPEC>

0x158 - SPI1 external RAM ACE section 2 start address register

pub fn spi_smem_pms3_size(&self) -> &Reg<SPI_SMEM_PMS_SIZE_SPEC>

0x15c - SPI1 external RAM ACE section 3 start address register

pub fn pms_reject(&self) -> &Reg<PMS_REJECT_SPEC>

0x164 - SPI1 access reject register

pub fn ecc_ctrl(&self) -> &Reg<ECC_CTRL_SPEC>

0x168 - MSPI ECC control register

pub fn ecc_err_addr(&self) -> &Reg<ECC_ERR_ADDR_SPEC>

0x16c - MSPI ECC error address register

pub fn axi_err_addr(&self) -> &Reg<AXI_ERR_ADDR_SPEC>

0x170 - SPI0 AXI request error address.

pub fn spi_smem_ecc_ctrl(&self) -> &Reg<SPI_SMEM_ECC_CTRL_SPEC>

0x174 - MSPI ECC control register

pub fn timing_cali(&self) -> &Reg<TIMING_CALI_SPEC>

0x180 - SPI0 flash timing calibration register

pub fn din_mode(&self) -> &Reg<DIN_MODE_SPEC>

0x184 - MSPI flash input timing delay mode control register

pub fn din_num(&self) -> &Reg<DIN_NUM_SPEC>

0x188 - MSPI flash input timing delay number control register

pub fn dout_mode(&self) -> &Reg<DOUT_MODE_SPEC>

0x18c - MSPI flash output timing adjustment control register

pub fn spi_smem_timing_cali(&self) -> &Reg<SPI_SMEM_TIMING_CALI_SPEC>

0x190 - MSPI external RAM timing calibration register

pub fn spi_smem_din_mode(&self) -> &Reg<SPI_SMEM_DIN_MODE_SPEC>

0x194 - MSPI external RAM input timing delay mode control register

pub fn spi_smem_din_num(&self) -> &Reg<SPI_SMEM_DIN_NUM_SPEC>

0x198 - MSPI external RAM input timing delay number control register

pub fn spi_smem_dout_mode(&self) -> &Reg<SPI_SMEM_DOUT_MODE_SPEC>

0x19c - MSPI external RAM output timing adjustment control register

pub fn spi_smem_ac(&self) -> &Reg<SPI_SMEM_AC_SPEC>

0x1a0 - MSPI external RAM ECC and SPI CS timing control register

pub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>

0x200 - SPI0 clock gate register

pub fn xts_plain_base(&self) -> &Reg<XTS_PLAIN_BASE_SPEC>

0x300 - The base address of the memory that stores plaintext in Manual Encryption

pub fn xts_linesize(&self) -> &Reg<XTS_LINESIZE_SPEC>

0x340 - Manual Encryption Line-Size register

pub fn xts_destination(&self) -> &Reg<XTS_DESTINATION_SPEC>

0x344 - Manual Encryption destination register

pub fn xts_physical_address(&self) -> &Reg<XTS_PHYSICAL_ADDRESS_SPEC>

0x348 - Manual Encryption physical address register

pub fn xts_trigger(&self) -> &Reg<XTS_TRIGGER_SPEC>

0x34c - Manual Encryption physical address register

pub fn xts_release(&self) -> &Reg<XTS_RELEASE_SPEC>

0x350 - Manual Encryption physical address register

pub fn xts_destroy(&self) -> &Reg<XTS_DESTROY_SPEC>

0x354 - Manual Encryption physical address register

pub fn xts_state(&self) -> &Reg<XTS_STATE_SPEC>

0x358 - Manual Encryption physical address register

pub fn xts_date(&self) -> &Reg<XTS_DATE_SPEC>

0x35c - Manual Encryption version register

pub fn mmu_item_content(&self) -> &Reg<MMU_ITEM_CONTENT_SPEC>

0x37c - MSPI-MMU item content register

pub fn mmu_item_index(&self) -> &Reg<MMU_ITEM_INDEX_SPEC>

0x380 - MSPI-MMU item index register

pub fn mmu_power_ctrl(&self) -> &Reg<MMU_POWER_CTRL_SPEC>

0x384 - MSPI MMU power control register

pub fn dpa_ctrl(&self) -> &Reg<DPA_CTRL_SPEC>

0x388 - SPI memory cryption DPA register

pub fn registerrnd_eco_high(&self) -> &Reg<REGISTERRND_ECO_HIGH_SPEC>

0x3f0 - MSPI ECO high register

pub fn registerrnd_eco_low(&self) -> &Reg<REGISTERRND_ECO_LOW_SPEC>

0x3f4 - MSPI ECO low register

pub fn date(&self) -> &Reg<DATE_SPEC>

0x3fc - SPI0 version control register

Trait Implementations

impl Debug for SPI0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for SPI0

type Target = <SPI0 as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for SPI0

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl Peripheral for SPI0

type P = SPI0

Peripheral singleton type

unsafe fn clone_unchecked(&self) -> Self::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.

fn map_into<U>(self) -> U

where Self::P: Into<U>, U: Peripheral<P = U>,

Map the peripheral using Into.