Enum MdcClockDivider 

pub enum MdcClockDivider {
    Div16 = 2,
    Div26 = 3,
    Div42 = 0,
    Div62 = 1,
    Div102 = 4,
    Div124 = 5,
}

MDC clock divider based on system clock frequency.

The MDC clock must not exceed 2.5 MHz per IEEE 802.3.

Variants

Div16 = 2

Clock/16 (20-35 MHz system clock)

Div26 = 3

Clock/26 (35-60 MHz system clock)

Div42 = 0

Clock/42 (60-100 MHz system clock) — ESP32 @ 80 MHz

Div62 = 1

Clock/62 (100-150 MHz system clock)

Div102 = 4

Clock/102 (150-250 MHz system clock)

Div124 = 5

Clock/124 (250-300 MHz system clock)

Implementations

impl MdcClockDivider

pub const fn from_sys_clock_hz(hz: u32) -> Self

Select the appropriate divider for a given system clock frequency.

pub const fn reg_value(self) -> u32

Get the register value for this divider.

Trait Implementations

impl Clone for MdcClockDivider

fn clone(&self) -> MdcClockDivider

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for MdcClockDivider

impl Debug for MdcClockDivider

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for MdcClockDivider

fn default() -> Self

Default: Div42 (correct for ESP32 @ 80 MHz).

impl Eq for MdcClockDivider

impl Format for MdcClockDivider

fn format(&self, f: Formatter<'_>)

Writes the defmt representation of self to fmt.

impl PartialEq for MdcClockDivider

fn eq(&self, other: &MdcClockDivider) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for MdcClockDivider