#[repr(C)]pub struct RegisterBlock {Show 21 fields
pub wdogload: Reg<WDOGLOAD_SPEC>,
pub wdogvalue: Reg<WDOGVALUE_SPEC>,
pub wdogcontrol: Reg<WDOGCONTROL_SPEC>,
pub wdogintclr: Reg<WDOGINTCLR_SPEC>,
pub wdogris: Reg<WDOGRIS_SPEC>,
pub wdogmis: Reg<WDOGMIS_SPEC>,
pub wdoglock: Reg<WDOGLOCK_SPEC>,
pub wdogitcr: Reg<WDOGITCR_SPEC>,
pub wdogitop: Reg<WDOGITOP_SPEC>,
pub wdogperiphid4: Reg<WDOGPERIPHID4_SPEC>,
pub wdogperiphid5: Reg<WDOGPERIPHID5_SPEC>,
pub wdogperiphid6: Reg<WDOGPERIPHID6_SPEC>,
pub wdogperiphid7: Reg<WDOGPERIPHID7_SPEC>,
pub wdogperiphid0: Reg<WDOGPERIPHID0_SPEC>,
pub wdogperiphid1: Reg<WDOGPERIPHID1_SPEC>,
pub wdogperiphid2: Reg<WDOGPERIPHID2_SPEC>,
pub wdogperiphid3: Reg<WDOGPERIPHID3_SPEC>,
pub wdogpcellid0: Reg<WDOGPCELLID0_SPEC>,
pub wdogpcellid1: Reg<WDOGPCELLID1_SPEC>,
pub wdogpcellid2: Reg<WDOGPCELLID2_SPEC>,
pub wdogpcellid3: Reg<WDOGPCELLID3_SPEC>,
/* private fields */
}Expand description
Register block
Fields§
§wdogload: Reg<WDOGLOAD_SPEC>0x00 - The WDOGLOAD Register contains the value from which the counter is to decrement. When this register is written to, the count is immediately restarted from the new value. The minimum valid value for WDOGLOAD is 1.
wdogvalue: Reg<WDOGVALUE_SPEC>0x04 - The WDOGVALUE Register gives the current value of the decrementing counter.
wdogcontrol: Reg<WDOGCONTROL_SPEC>0x08 - Control register for the WatchDog timer
wdogintclr: Reg<WDOGINTCLR_SPEC>0x0c - A write of any value to the WDOGINTCLR Register clears the watchdog interrupt, and reloads the counter from the value in WDOGLOAD.
wdogris: Reg<WDOGRIS_SPEC>0x10 - The WDOGRIS Register indicates the raw interrupt status from the counter. This value is ANDed with the interrupt enable bit from the control register to create the masked interrupt, that is passed to the interrupt output pin.
wdogmis: Reg<WDOGMIS_SPEC>0x14 - The WDOGMIS Register indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the INTEN bit from the control register, and is the same value that is passed to the interrupt output pin. Enabled interrupt status from the counter.
wdoglock: Reg<WDOGLOCK_SPEC>0xc00 - The WDOGLOCK Register diables write accesses to all other registers. This is to prevent rogue software from diabling the watchdog functionality. Writing a value 0x1ACCE551 enables write access to all other registers. Writing any other value disables write accesses.
wdogitcr: Reg<WDOGITCR_SPEC>0xf00 - The WDOGITCR Register enables integration test mode. When in this more, the test output register directly controls the masted interrup output, WDOGINT, and reset output, WDOGRES. Integration Test mode Enable [0] When set HIGH, places th watchdog into integration test mode.
wdogitop: Reg<WDOGITOP_SPEC>0xf04 - Watchdog Integration Test Output Set Register When the WDOGITOP Register is in integration test mode, the values in this register directly drive the enabled interrupt output and reset output.
wdogperiphid4: Reg<WDOGPERIPHID4_SPEC>0xfd0 - Peripheral ID Register 4: [7:4] Block count. [3:0] jep106_c_code.
wdogperiphid5: Reg<WDOGPERIPHID5_SPEC>0xfd4 - Peripheral ID Register 5.
wdogperiphid6: Reg<WDOGPERIPHID6_SPEC>0xfd8 - Peripheral ID Register 6.
wdogperiphid7: Reg<WDOGPERIPHID7_SPEC>0xfdc - Peripheral ID Register 7.
wdogperiphid0: Reg<WDOGPERIPHID0_SPEC>0xfe0 - Periperhal ID Register 0. [7:0] Part number[7:0].
wdogperiphid1: Reg<WDOGPERIPHID1_SPEC>0xfe4 - Peripheral ID Register 1. [7:4] jep106_id_3_0. [3:0] Part number [11:8].
wdogperiphid2: Reg<WDOGPERIPHID2_SPEC>0xfe8 - Peripheral ID Register 2. [7:4] Revision. [3] jedec_used. [2:0] jep106_id_6_4.
wdogperiphid3: Reg<WDOGPERIPHID3_SPEC>0xfec - Peripherial ID Register 3. [7:4] ECO revision number. [3:0] Customer modification number.
wdogpcellid0: Reg<WDOGPCELLID0_SPEC>0xff0 - Component ID Register 0.
wdogpcellid1: Reg<WDOGPCELLID1_SPEC>0xff4 - Component ID Register 1.
wdogpcellid2: Reg<WDOGPCELLID2_SPEC>0xff8 - Component ID Register 2.
wdogpcellid3: Reg<WDOGPCELLID3_SPEC>0xffc - Component ID Register 3.