#[repr(C)]pub struct RegisterBlock {Show 77 fields
pub misc_por_0: Reg<MISC_POR_0_SPEC>,
pub misc_por_1: Reg<MISC_POR_1_SPEC>,
pub misc_por_2: Reg<MISC_POR_2_SPEC>,
pub misc_por_3: Reg<MISC_POR_3_SPEC>,
pub rst_ctrl_0: Reg<RST_CTRL_0_SPEC>,
pub rst_ctrl_1: Reg<RST_CTRL_1_SPEC>,
pub chip_sta_0: Reg<CHIP_STA_0_SPEC>,
pub chip_sta_1: Reg<CHIP_STA_1_SPEC>,
pub wic_ctrl: Reg<WIC_CTRL_SPEC>,
pub wic_status: Reg<WIC_STATUS_SPEC>,
pub pwr_dwn_sch: Reg<PWR_DWN_SCH_SPEC>,
pub pwr_off_osc: Reg<PWR_OFF_OSC_SPEC>,
pub ext_waking_up_src: Reg<EXT_WAKING_UP_SRC_SPEC>,
pub sdma_status: Reg<SDMA_STATUS_SPEC>,
pub sdma_power_mode_cfg: Reg<SDMA_POWER_MODE_CFG_SPEC>,
pub sdma_pd_src_mask_n: Reg<SDMA_PD_SRC_MASK_N_SPEC>,
pub sdma_wu_src_mask_n: Reg<SDMA_WU_SRC_MASK_N_SPEC>,
pub m4_pwr_mode_cfg: Reg<M4_PWR_MODE_CFG_SPEC>,
pub m4_pd_src_maskk_n: Reg<M4_PD_SRC_MASKK_N_SPEC>,
pub m4_wu: Reg<M4_WU_SPEC>,
pub ffe_status: Reg<FFE_STATUS_SPEC>,
pub ffe_pwr_mode_cfg: Reg<FFE_PWR_MODE_CFG_SPEC>,
pub ffe_pd_src_mask_n: Reg<FFE_PD_SRC_MASK_N_SPEC>,
pub ffe_wu_src_mask_n: Reg<FFE_WU_SRC_MASK_N_SPEC>,
pub fb_status: Reg<FB_STATUS_SPEC>,
pub fb_pwr_mode_cfg: Reg<FB_PWR_MODE_CFG_SPEC>,
pub fb_pd_src_mask_n: Reg<FB_PD_SRC_MASK_N_SPEC>,
pub fb_wu_src_mask_n: Reg<FB_WU_SRC_MASK_N_SPEC>,
pub pf_pwr_mode_cfg: Reg<PF_PWR_MODE_CFG_SPEC>,
pub pf_pd_src_mask_n: Reg<PF_PD_SRC_MASK_N_SPEC>,
pub pf_wu_src_mask_n: Reg<PF_WU_SRC_MASK_N_SPEC>,
pub m4s0_sram_status: Reg<M4S0_SRAM_STATUS_SPEC>,
pub m4s0_pwr_mode_cfg: Reg<M4S0_PWR_MODE_CFG_SPEC>,
pub m4s0_pd_src_mask_n: Reg<M4S0_PD_SRC_MASK_N_SPEC>,
pub m4s0_wu_src_mask_n: Reg<M4S0_WU_SRC_MASK_N_SPEC>,
pub a1_status: Reg<A1_STATUS_SPEC>,
pub a1_pwr_mode_cfg: Reg<A1_PWR_MODE_CFG_SPEC>,
pub a1_pd_src_mask_n: Reg<A1_PD_SRC_MASK_N_SPEC>,
pub a1_wu_src_mask_n: Reg<A1_WU_SRC_MASK_N_SPEC>,
pub misc_status: Reg<MISC_STATUS_SPEC>,
pub audio_status: Reg<AUDIO_STATUS_SPEC>,
pub m4_sram_status: Reg<M4_SRAM_STATUS_SPEC>,
pub audio_wu_src_mask_n: Reg<AUDIO_WU_SRC_MASK_N_SPEC>,
pub m4_mem_ctrl_0: Reg<M4_MEM_CTRL_0_SPEC>,
pub m4_mem_ctrl_1: Reg<M4_MEM_CTRL_1_SPEC>,
pub pf_mem_ctrl_0: Reg<PF_MEM_CTRL_0_SPEC>,
pub pf_mem_ctrl_1: Reg<PF_MEM_CTRL_1_SPEC>,
pub ffe_mem_ctrl_0: Reg<FFE_MEM_CTRL_0_SPEC>,
pub ffe_mem_ctrl_1: Reg<FFE_MEM_CTRL_1_SPEC>,
pub audio_mem_ctrl_0: Reg<AUDIO_MEM_CTRL_0_SPEC>,
pub audio_mem_ctrl_1: Reg<AUDIO_MEM_CTRL_1_SPEC>,
pub m4_mem_cfg: Reg<M4_MEM_CFG_SPEC>,
pub pf_mem_cfg: Reg<PF_MEM_CFG_SPEC>,
pub ffe_mem_cfg: Reg<FFE_MEM_CFG_SPEC>,
pub audio_mem_cfg: Reg<AUDIO_MEM_CFG_SPEC>,
pub m4_mem_ctrl_pwr_0: Reg<M4_MEM_CTRL_PWR_0_SPEC>,
pub m4_mem_ctrl_pwr_1: Reg<M4_MEM_CTRL_PWR_1_SPEC>,
pub m4_mem_ctrl_pwr_2: Reg<M4_MEM_CTRL_PWR_2_SPEC>,
pub sdma_mem_ctrl_0: Reg<SDMA_MEM_CTRL_0_SPEC>,
pub sdma_mem_ctrl_1: Reg<SDMA_MEM_CTRL_1_SPEC>,
pub mem_pwr_dwn_ctrl: Reg<MEM_PWR_DWN_CTRL_SPEC>,
pub pmu_timer_cfg_0: Reg<PMU_TIMER_CFG_0_SPEC>,
pub pmu_timer_cfg_1: Reg<PMU_TIMER_CFG_1_SPEC>,
pub pdwu_timer_cfg: Reg<PDWU_TIMER_CFG_SPEC>,
pub ffe_fb_pf_sw_pd: Reg<FFE_FB_PF_SW_PD_SPEC>,
pub m4_sram_sw_pd: Reg<M4_SRAM_SW_PD_SPEC>,
pub misc_sw_pd: Reg<MISC_SW_PD_SPEC>,
pub audio_sw_pd: Reg<AUDIO_SW_PD_SPEC>,
pub ffe_fb_pf_sw_wu: Reg<FFE_FB_PF_SW_WU_SPEC>,
pub m4_sram_sw_wu: Reg<M4_SRAM_SW_WU_SPEC>,
pub misc_sw_wu: Reg<MISC_SW_WU_SPEC>,
pub audio_sram_sw_wu: Reg<AUDIO_SRAM_SW_WU_SPEC>,
pub pmu_stm_priority: Reg<PMU_STM_PRIORITY_SPEC>,
pub m4sram_ssw_lpmf: Reg<M4SRAM_SSW_LPMF_SPEC>,
pub m4sram_ssw_lpmh_mask_n: Reg<M4SRAM_SSW_LPMH_MASK_N_SPEC>,
pub fbvlpmin_width: Reg<FBVLPMINWIDTH_SPEC>,
pub apreboot_status: Reg<APREBOOTSTATUS_SPEC>,
/* private fields */
}Expand description
Register block
Fields§
§misc_por_0: Reg<MISC_POR_0_SPEC>0x00 - On POR Reset Domain
misc_por_1: Reg<MISC_POR_1_SPEC>0x04 - On POR Reset Domain
misc_por_2: Reg<MISC_POR_2_SPEC>0x08 - On POR Reset Domain
misc_por_3: Reg<MISC_POR_3_SPEC>0x0c - On POR Reset Domain
rst_ctrl_0: Reg<RST_CTRL_0_SPEC>0x10 - Reserved
rst_ctrl_1: Reg<RST_CTRL_1_SPEC>0x14 - Reserved
chip_sta_0: Reg<CHIP_STA_0_SPEC>0x18 - Reserved
chip_sta_1: Reg<CHIP_STA_1_SPEC>0x1c - Chip Status register
wic_ctrl: Reg<WIC_CTRL_SPEC>0x20 - Wake-up Interrupt Controller control register
wic_status: Reg<WIC_STATUS_SPEC>0x24 - Wake-up Interrupt Controller Status register
pwr_dwn_sch: Reg<PWR_DWN_SCH_SPEC>0x30 - Power Down Scheme configuration
pwr_off_osc: Reg<PWR_OFF_OSC_SPEC>0x40 - Control the power state of Oscillator once the M4 is in Power Saving Mode
ext_waking_up_src: Reg<EXT_WAKING_UP_SRC_SPEC>0x44 - Configure the external wakeup event source. Turn on the OSC once PMUT is time out or GPIO INT is triggering.
sdma_status: Reg<SDMA_STATUS_SPEC>0x70 - SDMA status register
sdma_power_mode_cfg: Reg<SDMA_POWER_MODE_CFG_SPEC>0x74 - Register for SDMA Power Mode configuration
sdma_pd_src_mask_n: Reg<SDMA_PD_SRC_MASK_N_SPEC>0x78 - Register for controlling if power down event will be masked
sdma_wu_src_mask_n: Reg<SDMA_WU_SRC_MASK_N_SPEC>0x7c - Reserved
m4_pwr_mode_cfg: Reg<M4_PWR_MODE_CFG_SPEC>0x84 - Configuration for the M4 power domain
m4_pd_src_maskk_n: Reg<M4_PD_SRC_MASKK_N_SPEC>0x88 - Reserved
m4_wu: Reg<M4_WU_SPEC>0x8c - Reserved
ffe_status: Reg<FFE_STATUS_SPEC>0x90 - Status of the Flexible Fusion Engine
ffe_pwr_mode_cfg: Reg<FFE_PWR_MODE_CFG_SPEC>0x94 - Power Mode configuration for the Flexible Fusion Engine Power Domain
ffe_pd_src_mask_n: Reg<FFE_PD_SRC_MASK_N_SPEC>0x98 - Control masking of busy signal. The falling edge of any of the above signals (non-mask) will put the FFE into Power saving mode base on the Power Mode Cfg. Note: These signals used to indicate the BUSY status, so they must be level signals.
ffe_wu_src_mask_n: Reg<FFE_WU_SRC_MASK_N_SPEC>0x9c - Control the masking of the Flexible Fusion Engine wake-up event triggers
fb_status: Reg<FB_STATUS_SPEC>0xa0 - FPGA Fabric Power domain status
fb_pwr_mode_cfg: Reg<FB_PWR_MODE_CFG_SPEC>0xa4 - Power mode configuration for the FPGA Fabric Power domain
fb_pd_src_mask_n: Reg<FB_PD_SRC_MASK_N_SPEC>0xa8 - Control masking of power down event signals for the FPGA Fabric power domain. The falling edge of any of the listed signals (non-mask) will put the FB into Power saving mode base on the Power Mode Cfg. Note: These signals used to indicate the BUSY status, so they must be level signals.
fb_wu_src_mask_n: Reg<FB_WU_SRC_MASK_N_SPEC>0xac - Control the masking of the FPGA FAbric wake-up event triggers
pf_pwr_mode_cfg: Reg<PF_PWR_MODE_CFG_SPEC>0xb4 - Power mode configuration for the PF SRAM Power domain
pf_pd_src_mask_n: Reg<PF_PD_SRC_MASK_N_SPEC>0xb8 - Reserved
pf_wu_src_mask_n: Reg<PF_WU_SRC_MASK_N_SPEC>0xbc - Reserved
m4s0_sram_status: Reg<M4S0_SRAM_STATUS_SPEC>0xc0 - M4S0 SRAM Power Domain status
m4s0_pwr_mode_cfg: Reg<M4S0_PWR_MODE_CFG_SPEC>0xc4 - Power mode configuration for the M4S0 SRAM power domain
m4s0_pd_src_mask_n: Reg<M4S0_PD_SRC_MASK_N_SPEC>0xc8 - Control masking of power-down event triggers for the M4S0 SRAM domain
m4s0_wu_src_mask_n: Reg<M4S0_WU_SRC_MASK_N_SPEC>0xcc - Control masking of wake-up event triggers for the M4S0 SRAM domain
a1_status: Reg<A1_STATUS_SPEC>0xd0 - Status of the A1 power domain
a1_pwr_mode_cfg: Reg<A1_PWR_MODE_CFG_SPEC>0xd4 - Power mode configuration for the A1 power domain
a1_pd_src_mask_n: Reg<A1_PD_SRC_MASK_N_SPEC>0xd8 - Reserved
a1_wu_src_mask_n: Reg<A1_WU_SRC_MASK_N_SPEC>0xdc - Control masking of wake-up event triggers for the A1 domain
misc_status: Reg<MISC_STATUS_SPEC>0xe0 - I2S Power info
audio_status: Reg<AUDIO_STATUS_SPEC>0xe4 - Audio power domain status
m4_sram_status: Reg<M4_SRAM_STATUS_SPEC>0xe8 - M4 SRAM Power domain status
audio_wu_src_mask_n: Reg<AUDIO_WU_SRC_MASK_N_SPEC>0xec - Control masking of wake-up event triggers for the Audio domains
m4_mem_ctrl_0: Reg<M4_MEM_CTRL_0_SPEC>0x100 - Control DS pins for different SRAM instances on the M4 subsystem. For each instance: 1’b1 : Enable the Deep Sleep funciton of SRAM Macro, Memory content will be kept. While M4 access the memory in Deep Sleep mode, the HW will clear the corresponding bit.
m4_mem_ctrl_1: Reg<M4_MEM_CTRL_1_SPEC>0x104 - Control Shutdown pin for various instances of SRAM on the M4 subsystem. For each instance: 1’b1 : Enable the Shutdown funciton of SRAM Macro, Memory content will be lost. While M4 access the memory in Shutdown mode, the HW will clear the corresponding bit.
pf_mem_ctrl_0: Reg<PF_MEM_CTRL_0_SPEC>0x108 - RESERVED
pf_mem_ctrl_1: Reg<PF_MEM_CTRL_1_SPEC>0x10c - Control Shut Down pin of various FIFOs intances in the PF subsystem. For each one: 1’b1 : Enable the Shut Down function of SRAM Macro, Memory content will be lost
ffe_mem_ctrl_0: Reg<FFE_MEM_CTRL_0_SPEC>0x110 - Control the Deep Sleep pin of various elements in the Flexible Fusion Engine power domain. For each: 1’b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept.
ffe_mem_ctrl_1: Reg<FFE_MEM_CTRL_1_SPEC>0x114 - Control the Shut Down pin of various elements in the Flexible Fusion Engine power domain. For each: 1’b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept.
audio_mem_ctrl_0: Reg<AUDIO_MEM_CTRL_0_SPEC>0x118 - Control the Deep Sleep pin of Audio channels. For each: 1’b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept.
audio_mem_ctrl_1: Reg<AUDIO_MEM_CTRL_1_SPEC>0x11c - Control the shut down pin of Audio channels. For each: 1’b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept.
m4_mem_cfg: Reg<M4_MEM_CFG_SPEC>0x120 - Reserved
pf_mem_cfg: Reg<PF_MEM_CFG_SPEC>0x124 - Reserved
ffe_mem_cfg: Reg<FFE_MEM_CFG_SPEC>0x128 - Control Light Sleep pin of different FFE SRAM power domains
audio_mem_cfg: Reg<AUDIO_MEM_CFG_SPEC>0x12c - Reserved
m4_mem_ctrl_pwr_0: Reg<M4_MEM_CTRL_PWR_0_SPEC>0x130 - Reserved
m4_mem_ctrl_pwr_1: Reg<M4_MEM_CTRL_PWR_1_SPEC>0x134 - Reserved
m4_mem_ctrl_pwr_2: Reg<M4_MEM_CTRL_PWR_2_SPEC>0x138 - Reserved
sdma_mem_ctrl_0: Reg<SDMA_MEM_CTRL_0_SPEC>0x140 - Control the Deep Sleep function of SRAM Macro for the SDMA power domain
sdma_mem_ctrl_1: Reg<SDMA_MEM_CTRL_1_SPEC>0x144 - Control the Shut Down function of SRAM Macro for the SDMA power domain
mem_pwr_dwn_ctrl: Reg<MEM_PWR_DWN_CTRL_SPEC>0x180 - Memory Power Down Control
pmu_timer_cfg_0: Reg<PMU_TIMER_CFG_0_SPEC>0x184 - Configuration for the PMU timer time-out period
pmu_timer_cfg_1: Reg<PMU_TIMER_CFG_1_SPEC>0x188 - Control wether the PMU timer is enabled or disabled
pdwu_timer_cfg: Reg<PDWU_TIMER_CFG_SPEC>0x18c - Control the delay for power-on after wake-up event. Applies to all power domains
ffe_fb_pf_sw_pd: Reg<FFE_FB_PF_SW_PD_SPEC>0x200 - Registers for triggering power-down events in the FFE, FB and PF power domains.
m4_sram_sw_pd: Reg<M4_SRAM_SW_PD_SPEC>0x204 - Register for triggering power-down events in M4 SRAM power domains. (RWHC)
misc_sw_pd: Reg<MISC_SW_PD_SPEC>0x208 - Register for triggering power down events in MISC power domains + some general purpose SFR’s (RWHC)
audio_sw_pd: Reg<AUDIO_SW_PD_SPEC>0x20c - Register for triggering power-down events in Audio power domains. (RWHC)
ffe_fb_pf_sw_wu: Reg<FFE_FB_PF_SW_WU_SPEC>0x210 - Registers for triggering wake-up events in the FFE, FB and PF power domains.
m4_sram_sw_wu: Reg<M4_SRAM_SW_WU_SPEC>0x214 - Register for triggering wake-up events in M4 SRAM power domains. (RWHC)
misc_sw_wu: Reg<MISC_SW_WU_SPEC>0x218 - Register for triggering wake up events in MISC power domains + some general purpose SFR’s (RWHC)
audio_sram_sw_wu: Reg<AUDIO_SRAM_SW_WU_SPEC>0x21c - Register for triggering wake-up events in Audio power domains. (RWHC)
pmu_stm_priority: Reg<PMU_STM_PRIORITY_SPEC>0x220 - Power Management Unit Software Test Mode priority control
m4sram_ssw_lpmf: Reg<M4SRAM_SSW_LPMF_SPEC>0x230 - Control for M4SRAM power domain light sleep mode
m4sram_ssw_lpmh_mask_n: Reg<M4SRAM_SSW_LPMH_MASK_N_SPEC>0x234 - Control masking for the LPMH (Low Power Mode header - deep sleep circuit)
fbvlpmin_width: Reg<FBVLPMINWIDTH_SPEC>0x3e8 - Configuration for the amount of IDLE cycles before powering on the FB domain
apreboot_status: Reg<APREBOOTSTATUS_SPEC>0x3ec - Indicates if AP nees to reload the code to SRAM
Implementations§
Source§impl RegisterBlock
impl RegisterBlock
Sourcepub fn pf_status(&self) -> &Reg<PF_STATUS_SPEC>
pub fn pf_status(&self) -> &Reg<PF_STATUS_SPEC>
0x80 - PF SRAM Power Domain status
Sourcepub fn m4_status(&self) -> &Reg<M4_STATUS_SPEC>
pub fn m4_status(&self) -> &Reg<M4_STATUS_SPEC>
0x80 - Status of the M4 Power Domain
Sourcepub fn gen_purpose_0(&self) -> &Reg<GEN_PURPOSE_0_SPEC>
pub fn gen_purpose_0(&self) -> &Reg<GEN_PURPOSE_0_SPEC>
0x3f0 - Configure FB config enable and wether Audio SRAM can be put into Deep Sleep by the Audio hardware
Sourcepub fn gen_purpose_1(&self) -> &Reg<GEN_PURPOSE_1_SPEC>
pub fn gen_purpose_1(&self) -> &Reg<GEN_PURPOSE_1_SPEC>
0x3f3 - Control for: Wether ext-interrupt can be used to wake up FFE, and clock switching for FFE/M4 power domains
Sourcepub fn fb_isolation(&self) -> &Reg<FB_ISOLATION_SPEC>
pub fn fb_isolation(&self) -> &Reg<FB_ISOLATION_SPEC>
0x3f4 - Control the FB Isolation