#[repr(C)]pub struct RegisterBlock {Show 28 fields
pub addr: Reg<ADDR_SPEC>,
pub wdata: Reg<WDATA_SPEC>,
pub csr: Reg<CSR_SPEC>,
pub rdata: Reg<RDATA_SPEC>,
pub sram_test_reg1: Reg<SRAM_TEST_REG1_SPEC>,
pub sram_test_reg2: Reg<SRAM_TEST_REG2_SPEC>,
pub ffe_csr: Reg<FFE_CSR_SPEC>,
pub ffe_dbg_combined: Reg<FFE_DBG_COMBINED_SPEC>,
pub cmd: Reg<CMD_SPEC>,
pub interrupt: Reg<INTERRUPT_SPEC>,
pub interrupt_en: Reg<INTERRUPT_EN_SPEC>,
pub status: Reg<STATUS_SPEC>,
pub mailbox_to_ffe0: Reg<MAILBOX_TO_FFE0_SPEC>,
pub sm_runtime_addr: Reg<SM_RUNTIME_ADDR_SPEC>,
pub sm0_runtime_addr_ctrl: Reg<SM0_RUNTIME_ADDR_CTRL_SPEC>,
pub sm1_runtime_addr_ctrl: Reg<SM1_RUNTIME_ADDR_CTRL_SPEC>,
pub sm0_runtime_addr_cur: Reg<SM0_RUNTIME_ADDR_CUR_SPEC>,
pub sm1_runtime_addr_cur: Reg<SM1_RUNTIME_ADDR_CUR_SPEC>,
pub sm0_debug_sel: Reg<SM0_DEBUG_SEL_SPEC>,
pub sm1_debug_sel: Reg<SM1_DEBUG_SEL_SPEC>,
pub ffe_debug_sel: Reg<FFE_DEBUG_SEL_SPEC>,
pub ffe0_break_point_cfg: Reg<FFE0_BREAK_POINT_CFG_SPEC>,
pub ffe0_break_point_cont: Reg<FFE0_BREAK_POINT_CONT_SPEC>,
pub ffe0_break_point_stat: Reg<FFE0_BREAK_POINT_STAT_SPEC>,
pub ffe0_bp_xpc_0: Reg<FFE0_BP_XPC_0_SPEC>,
pub ffe0_bp_xpc_1: Reg<FFE0_BP_XPC_1_SPEC>,
pub ffe0_bp_xpc_2: Reg<FFE0_BP_XPC_2_SPEC>,
pub ffe0_bp_xpc_3: Reg<FFE0_BP_XPC_3_SPEC>,
/* private fields */
}Expand description
Register block
Fields§
§addr: Reg<ADDR_SPEC>0x00 - Wishbone master address selection
wdata: Reg<WDATA_SPEC>0x04 - I2C slave data register via WishBone master
csr: Reg<CSR_SPEC>0x08 - Control and status register
rdata: Reg<RDATA_SPEC>0x0c - Read data from I2C to Wishbone master is registered
sram_test_reg1: Reg<SRAM_TEST_REG1_SPEC>0x14 - SRAM test control register 1
sram_test_reg2: Reg<SRAM_TEST_REG2_SPEC>0x18 - SRAM test control register 2
ffe_csr: Reg<FFE_CSR_SPEC>0x20 - Flexible Fusion Engine status and control register
ffe_dbg_combined: Reg<FFE_DBG_COMBINED_SPEC>0x38 - Combined Flexible Fusion Engine debug signals
cmd: Reg<CMD_SPEC>0x100 - Commands for the Flexible Fusion Engine
interrupt: Reg<INTERRUPT_SPEC>0x108 - Varied interrupt configurations
interrupt_en: Reg<INTERRUPT_EN_SPEC>0x10c - Control the masking for different Flexible Fusion Engine interrupts
status: Reg<STATUS_SPEC>0x110 - FFE status register
mailbox_to_ffe0: Reg<MAILBOX_TO_FFE0_SPEC>0x114 - Mailbox register to the FFE. This register can be set by system software to send a message or configuration information to the FFE as it runs its algorithm, thus affecting the algorithm while it is running. A special instruction may be used in the algorithm to read this mailbox register.
sm_runtime_addr: Reg<SM_RUNTIME_ADDR_SPEC>0x120 - SM0/SM1 run time address
sm0_runtime_addr_ctrl: Reg<SM0_RUNTIME_ADDR_CTRL_SPEC>0x124 - Used to toggle signal used to signal when a new value has been written.
sm1_runtime_addr_ctrl: Reg<SM1_RUNTIME_ADDR_CTRL_SPEC>0x128 - Used to toggle signal used to signal when a new value has been written.
sm0_runtime_addr_cur: Reg<SM0_RUNTIME_ADDR_CUR_SPEC>0x12c - SM current program counter
sm1_runtime_addr_cur: Reg<SM1_RUNTIME_ADDR_CUR_SPEC>0x130 - SM current program counter
sm0_debug_sel: Reg<SM0_DEBUG_SEL_SPEC>0x140 - SM Debug selection
sm1_debug_sel: Reg<SM1_DEBUG_SEL_SPEC>0x144 - SM Debug selection
ffe_debug_sel: Reg<FFE_DEBUG_SEL_SPEC>0x148 - Debug Selection
ffe0_break_point_cfg: Reg<FFE0_BREAK_POINT_CFG_SPEC>0x150 - Break point control
ffe0_break_point_cont: Reg<FFE0_BREAK_POINT_CONT_SPEC>0x154 - Seems to be another breakpoint control register
ffe0_break_point_stat: Reg<FFE0_BREAK_POINT_STAT_SPEC>0x158 - FFE break point status register
ffe0_bp_xpc_0: Reg<FFE0_BP_XPC_0_SPEC>0x160 - These registers hold the xPC (program counter) address ‘break points’.
ffe0_bp_xpc_1: Reg<FFE0_BP_XPC_1_SPEC>0x164 - These registers hold the xPC (program counter) address ‘break points’.
ffe0_bp_xpc_2: Reg<FFE0_BP_XPC_2_SPEC>0x168 - These registers hold the xPC (program counter) address ‘break points’.
ffe0_bp_xpc_3: Reg<FFE0_BP_XPC_3_SPEC>0x16c - These registers hold the xPC (program counter) address ‘break points’.