Trait embedded_hal_async::i2c::I2c
source · pub trait I2c<A: AddressMode = SevenBitAddress>: ErrorType {
async fn read<'a>(
&'a mut self,
address: A,
read: &'a mut [u8]
) -> Result<(), Self::Error>;
async fn write<'a>(
&'a mut self,
address: A,
write: &'a [u8]
) -> Result<(), Self::Error>;
async fn write_read<'a>(
&'a mut self,
address: A,
write: &'a [u8],
read: &'a mut [u8]
) -> Result<(), Self::Error>;
async fn transaction<'a, 'b>(
&'a mut self,
address: A,
operations: &'a mut [Operation<'b>]
) -> Result<(), Self::Error>;
}
Expand description
Async i2c
Required Methods
sourceasync fn read<'a>(
&'a mut self,
address: A,
read: &'a mut [u8]
) -> Result<(), Self::Error>
async fn read<'a>(
&'a mut self,
address: A,
read: &'a mut [u8]
) -> Result<(), Self::Error>
Reads enough bytes from slave with address
to fill buffer
I2C Events (contract)
Master: ST SAD+R MAK MAK ... NMAK SP
Slave: SAK B0 B1 ... BN
Where
ST
= start conditionSAD+R
= slave address followed by bit 1 to indicate readingSAK
= slave acknowledgeBi
= ith byte of dataMAK
= master acknowledgeNMAK
= master no acknowledgeSP
= stop condition
sourceasync fn write<'a>(
&'a mut self,
address: A,
write: &'a [u8]
) -> Result<(), Self::Error>
async fn write<'a>(
&'a mut self,
address: A,
write: &'a [u8]
) -> Result<(), Self::Error>
Writes bytes to slave with address address
I2C Events (contract)
Master: ST SAD+W B0 B1 ... BN SP
Slave: SAK SAK SAK ... SAK
Where
ST
= start conditionSAD+W
= slave address followed by bit 0 to indicate writingSAK
= slave acknowledgeBi
= ith byte of dataSP
= stop condition
sourceasync fn write_read<'a>(
&'a mut self,
address: A,
write: &'a [u8],
read: &'a mut [u8]
) -> Result<(), Self::Error>
async fn write_read<'a>(
&'a mut self,
address: A,
write: &'a [u8],
read: &'a mut [u8]
) -> Result<(), Self::Error>
Writes bytes to slave with address address
and then reads enough bytes to fill read
in a
single transaction.
I2C Events (contract)
Master: ST SAD+W O0 O1 ... OM SR SAD+R MAK MAK ... NMAK SP
Slave: SAK SAK SAK ... SAK SAK I0 I1 ... IN
Where
ST
= start conditionSAD+W
= slave address followed by bit 0 to indicate writingSAK
= slave acknowledgeOi
= ith outgoing byte of dataSR
= repeated start conditionSAD+R
= slave address followed by bit 1 to indicate readingIi
= ith incoming byte of dataMAK
= master acknowledgeNMAK
= master no acknowledgeSP
= stop condition
sourceasync fn transaction<'a, 'b>(
&'a mut self,
address: A,
operations: &'a mut [Operation<'b>]
) -> Result<(), Self::Error>
async fn transaction<'a, 'b>(
&'a mut self,
address: A,
operations: &'a mut [Operation<'b>]
) -> Result<(), Self::Error>
Execute the provided operations on the I2C bus as a single transaction.
Transaction contract:
-
Before executing the first operation an ST is sent automatically. This is followed by SAD+R/W as appropriate.
-
Data from adjacent operations of the same type are sent after each other without an SP or SR.
-
Between adjacent operations of a different type an SR and SAD+R/W is sent.
-
After executing the last operation an SP is sent automatically.
-
If the last operation is a
Read
the master does not send an acknowledge for the last byte. -
ST
= start condition -
SAD+R/W
= slave address followed by bit 1 to indicate reading or 0 to indicate writing -
SR
= repeated start condition -
SP
= stop condition