Struct efr32xg12p::prs::ch1_ctrl::_EDSELW
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pub struct _EDSELW<'a> { /* fields omitted */ }
Proxy
Methods
impl<'a> _EDSELW<'a>
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fn variant(self, variant: EDSELW) -> &'a mut W
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Writes variant
to the field
fn off(self) -> &'a mut W
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Signal is left as it is
fn posedge(self) -> &'a mut W
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A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
fn negedge(self) -> &'a mut W
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A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
fn bothedges(self) -> &'a mut W
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A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
fn bits(self, value: u8) -> &'a mut W
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Writes raw bits to the field