Struct efr32x12p::usart2::ctrl::R
[−]
[src]
pub struct R { /* fields omitted */ }
Value read from the register
Methods
impl R
[src]
fn bits(&self) -> u32
[src]
Value of the register as raw bits
fn sync(&self) -> SYNCR
[src]
Bit 0 - USART Synchronous Mode
fn loopbk(&self) -> LOOPBKR
[src]
Bit 1 - Loopback Enable
fn ccen(&self) -> CCENR
[src]
Bit 2 - Collision Check Enable
fn mpm(&self) -> MPMR
[src]
Bit 3 - Multi-Processor Mode
fn mpab(&self) -> MPABR
[src]
Bit 4 - Multi-Processor Address-Bit
fn ovs(&self) -> OVSR
[src]
Bits 5:6 - Oversampling
fn clkpol(&self) -> CLKPOLR
[src]
Bit 8 - Clock Polarity
fn clkpha(&self) -> CLKPHAR
[src]
Bit 9 - Clock Edge For Setup/Sample
fn msbf(&self) -> MSBFR
[src]
Bit 10 - Most Significant Bit First
fn csma(&self) -> CSMAR
[src]
Bit 11 - Action On Slave-Select In Master Mode
fn txbil(&self) -> TXBILR
[src]
Bit 12 - TX Buffer Interrupt Level
fn rxinv(&self) -> RXINVR
[src]
Bit 13 - Receiver Input Invert
fn txinv(&self) -> TXINVR
[src]
Bit 14 - Transmitter output Invert
fn csinv(&self) -> CSINVR
[src]
Bit 15 - Chip Select Invert
fn autocs(&self) -> AUTOCSR
[src]
Bit 16 - Automatic Chip Select
fn autotri(&self) -> AUTOTRIR
[src]
Bit 17 - Automatic TX Tristate
fn scmode(&self) -> SCMODER
[src]
Bit 18 - SmartCard Mode
fn scretrans(&self) -> SCRETRANSR
[src]
Bit 19 - SmartCard Retransmit
fn skipperrf(&self) -> SKIPPERRFR
[src]
Bit 20 - Skip Parity Error Frames
fn bit8dv(&self) -> BIT8DVR
[src]
Bit 21 - Bit 8 Default Value
fn errsdma(&self) -> ERRSDMAR
[src]
Bit 22 - Halt DMA On Error
fn errsrx(&self) -> ERRSRXR
[src]
Bit 23 - Disable RX On Error
fn errstx(&self) -> ERRSTXR
[src]
Bit 24 - Disable TX On Error
fn sssearly(&self) -> SSSEARLYR
[src]
Bit 25 - Synchronous Slave Setup Early
fn byteswap(&self) -> BYTESWAPR
[src]
Bit 28 - Byteswap In Double Accesses
fn autotx(&self) -> AUTOTXR
[src]
Bit 29 - Always Transmit When RX Not Full
fn mvdis(&self) -> MVDISR
[src]
Bit 30 - Majority Vote Disable
fn smsdelay(&self) -> SMSDELAYR
[src]
Bit 31 - Synchronous Master Sample Delay