RegisterBlock

efm32lg230_pac::dma

Struct RegisterBlock 

Source 
#[repr(C)]
pub struct RegisterBlock {
Show 40 fields
    pub status: Reg<STATUS_SPEC>,
    pub config: Reg<CONFIG_SPEC>,
    pub ctrlbase: Reg<CTRLBASE_SPEC>,
    pub altctrlbase: Reg<ALTCTRLBASE_SPEC>,
    pub chwaitstatus: Reg<CHWAITSTATUS_SPEC>,
    pub chswreq: Reg<CHSWREQ_SPEC>,
    pub chusebursts: Reg<CHUSEBURSTS_SPEC>,
    pub chuseburstc: Reg<CHUSEBURSTC_SPEC>,
    pub chreqmasks: Reg<CHREQMASKS_SPEC>,
    pub chreqmaskc: Reg<CHREQMASKC_SPEC>,
    pub chens: Reg<CHENS_SPEC>,
    pub chenc: Reg<CHENC_SPEC>,
    pub chalts: Reg<CHALTS_SPEC>,
    pub chaltc: Reg<CHALTC_SPEC>,
    pub chpris: Reg<CHPRIS_SPEC>,
    pub chpric: Reg<CHPRIC_SPEC>,
    pub errorc: Reg<ERRORC_SPEC>,
    pub chreqstatus: Reg<CHREQSTATUS_SPEC>,
    pub chsreqstatus: Reg<CHSREQSTATUS_SPEC>,
    pub if_: Reg<IF_SPEC>,
    pub ifs: Reg<IFS_SPEC>,
    pub ifc: Reg<IFC_SPEC>,
    pub ien: Reg<IEN_SPEC>,
    pub ctrl: Reg<CTRL_SPEC>,
    pub rds: Reg<RDS_SPEC>,
    pub loop0: Reg<LOOP0_SPEC>,
    pub loop1: Reg<LOOP1_SPEC>,
    pub rect0: Reg<RECT0_SPEC>,
    pub ch0_ctrl: Reg<CH0_CTRL_SPEC>,
    pub ch1_ctrl: Reg<CH1_CTRL_SPEC>,
    pub ch2_ctrl: Reg<CH2_CTRL_SPEC>,
    pub ch3_ctrl: Reg<CH3_CTRL_SPEC>,
    pub ch4_ctrl: Reg<CH4_CTRL_SPEC>,
    pub ch5_ctrl: Reg<CH5_CTRL_SPEC>,
    pub ch6_ctrl: Reg<CH6_CTRL_SPEC>,
    pub ch7_ctrl: Reg<CH7_CTRL_SPEC>,
    pub ch8_ctrl: Reg<CH8_CTRL_SPEC>,
    pub ch9_ctrl: Reg<CH9_CTRL_SPEC>,
    pub ch10_ctrl: Reg<CH10_CTRL_SPEC>,
    pub ch11_ctrl: Reg<CH11_CTRL_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields§

§status: Reg<STATUS_SPEC>

0x00 - DMA Status Registers

§config: Reg<CONFIG_SPEC>

0x04 - DMA Configuration Register

§ctrlbase: Reg<CTRLBASE_SPEC>

0x08 - Channel Control Data Base Pointer Register

§altctrlbase: Reg<ALTCTRLBASE_SPEC>

0x0c - Channel Alternate Control Data Base Pointer Register

§chwaitstatus: Reg<CHWAITSTATUS_SPEC>

0x10 - Channel Wait on Request Status Register

§chswreq: Reg<CHSWREQ_SPEC>

0x14 - Channel Software Request Register

§chusebursts: Reg<CHUSEBURSTS_SPEC>

0x18 - Channel Useburst Set Register

§chuseburstc: Reg<CHUSEBURSTC_SPEC>

0x1c - Channel Useburst Clear Register

§chreqmasks: Reg<CHREQMASKS_SPEC>

0x20 - Channel Request Mask Set Register

§chreqmaskc: Reg<CHREQMASKC_SPEC>

0x24 - Channel Request Mask Clear Register

§chens: Reg<CHENS_SPEC>

0x28 - Channel Enable Set Register

§chenc: Reg<CHENC_SPEC>

0x2c - Channel Enable Clear Register

§chalts: Reg<CHALTS_SPEC>

0x30 - Channel Alternate Set Register

§chaltc: Reg<CHALTC_SPEC>

0x34 - Channel Alternate Clear Register

§chpris: Reg<CHPRIS_SPEC>

0x38 - Channel Priority Set Register

§chpric: Reg<CHPRIC_SPEC>

0x3c - Channel Priority Clear Register

§errorc: Reg<ERRORC_SPEC>

0x4c - Bus Error Clear Register

§chreqstatus: Reg<CHREQSTATUS_SPEC>

0xe10 - Channel Request Status

§chsreqstatus: Reg<CHSREQSTATUS_SPEC>

0xe18 - Channel Single Request Status

§if_: Reg<IF_SPEC>

0x1000 - Interrupt Flag Register

§ifs: Reg<IFS_SPEC>

0x1004 - Interrupt Flag Set Register

§ifc: Reg<IFC_SPEC>

0x1008 - Interrupt Flag Clear Register

§ien: Reg<IEN_SPEC>

0x100c - Interrupt Enable register

§ctrl: Reg<CTRL_SPEC>

0x1010 - DMA Control Register

§rds: Reg<RDS_SPEC>

0x1014 - DMA Retain Descriptor State

§loop0: Reg<LOOP0_SPEC>

0x1020 - Channel 0 Loop Register

§loop1: Reg<LOOP1_SPEC>

0x1024 - Channel 1 Loop Register

§rect0: Reg<RECT0_SPEC>

0x1060 - Channel 0 Rectangle Register

§ch0_ctrl: Reg<CH0_CTRL_SPEC>

0x1100 - Channel Control Register

§ch1_ctrl: Reg<CH1_CTRL_SPEC>

0x1104 - Channel Control Register

§ch2_ctrl: Reg<CH2_CTRL_SPEC>

0x1108 - Channel Control Register

§ch3_ctrl: Reg<CH3_CTRL_SPEC>

0x110c - Channel Control Register

§ch4_ctrl: Reg<CH4_CTRL_SPEC>

0x1110 - Channel Control Register

§ch5_ctrl: Reg<CH5_CTRL_SPEC>

0x1114 - Channel Control Register

§ch6_ctrl: Reg<CH6_CTRL_SPEC>

0x1118 - Channel Control Register

§ch7_ctrl: Reg<CH7_CTRL_SPEC>

0x111c - Channel Control Register

§ch8_ctrl: Reg<CH8_CTRL_SPEC>

0x1120 - Channel Control Register

§ch9_ctrl: Reg<CH9_CTRL_SPEC>

0x1124 - Channel Control Register

§ch10_ctrl: Reg<CH10_CTRL_SPEC>

0x1128 - Channel Control Register

§ch11_ctrl: Reg<CH11_CTRL_SPEC>

0x112c - Channel Control Register

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