efm32hg310_pac::timer2

Struct RegisterBlock

Source 
#[repr(C)]
pub struct RegisterBlock {
Show 30 fields
    pub ctrl: Reg<CTRL_SPEC>,
    pub cmd: Reg<CMD_SPEC>,
    pub status: Reg<STATUS_SPEC>,
    pub ien: Reg<IEN_SPEC>,
    pub if_: Reg<IF_SPEC>,
    pub ifs: Reg<IFS_SPEC>,
    pub ifc: Reg<IFC_SPEC>,
    pub top: Reg<TOP_SPEC>,
    pub topb: Reg<TOPB_SPEC>,
    pub cnt: Reg<CNT_SPEC>,
    pub route: Reg<ROUTE_SPEC>,
    pub cc0_ctrl: Reg<CC0_CTRL_SPEC>,
    pub cc0_ccv: Reg<CC0_CCV_SPEC>,
    pub cc0_ccvp: Reg<CC0_CCVP_SPEC>,
    pub cc0_ccvb: Reg<CC0_CCVB_SPEC>,
    pub cc1_ctrl: Reg<CC1_CTRL_SPEC>,
    pub cc1_ccv: Reg<CC1_CCV_SPEC>,
    pub cc1_ccvp: Reg<CC1_CCVP_SPEC>,
    pub cc1_ccvb: Reg<CC1_CCVB_SPEC>,
    pub cc2_ctrl: Reg<CC2_CTRL_SPEC>,
    pub cc2_ccv: Reg<CC2_CCV_SPEC>,
    pub cc2_ccvp: Reg<CC2_CCVP_SPEC>,
    pub cc2_ccvb: Reg<CC2_CCVB_SPEC>,
    pub dtctrl: Reg<DTCTRL_SPEC>,
    pub dttime: Reg<DTTIME_SPEC>,
    pub dtfc: Reg<DTFC_SPEC>,
    pub dtogen: Reg<DTOGEN_SPEC>,
    pub dtfault: Reg<DTFAULT_SPEC>,
    pub dtfaultc: Reg<DTFAULTC_SPEC>,
    pub dtlock: Reg<DTLOCK_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields§

§ctrl: Reg<CTRL_SPEC>

0x00 - Control Register

§cmd: Reg<CMD_SPEC>

0x04 - Command Register

§status: Reg<STATUS_SPEC>

0x08 - Status Register

§ien: Reg<IEN_SPEC>

0x0c - Interrupt Enable Register

§if_: Reg<IF_SPEC>

0x10 - Interrupt Flag Register

§ifs: Reg<IFS_SPEC>

0x14 - Interrupt Flag Set Register

§ifc: Reg<IFC_SPEC>

0x18 - Interrupt Flag Clear Register

§top: Reg<TOP_SPEC>

0x1c - Counter Top Value Register

§topb: Reg<TOPB_SPEC>

0x20 - Counter Top Value Buffer Register

§cnt: Reg<CNT_SPEC>

0x24 - Counter Value Register

§route: Reg<ROUTE_SPEC>

0x28 - I/O Routing Register

§cc0_ctrl: Reg<CC0_CTRL_SPEC>

0x30 - CC Channel Control Register

§cc0_ccv: Reg<CC0_CCV_SPEC>

0x34 - CC Channel Value Register

§cc0_ccvp: Reg<CC0_CCVP_SPEC>

0x38 - CC Channel Value Peek Register

§cc0_ccvb: Reg<CC0_CCVB_SPEC>

0x3c - CC Channel Buffer Register

§cc1_ctrl: Reg<CC1_CTRL_SPEC>

0x40 - CC Channel Control Register

§cc1_ccv: Reg<CC1_CCV_SPEC>

0x44 - CC Channel Value Register

§cc1_ccvp: Reg<CC1_CCVP_SPEC>

0x48 - CC Channel Value Peek Register

§cc1_ccvb: Reg<CC1_CCVB_SPEC>

0x4c - CC Channel Buffer Register

§cc2_ctrl: Reg<CC2_CTRL_SPEC>

0x50 - CC Channel Control Register

§cc2_ccv: Reg<CC2_CCV_SPEC>

0x54 - CC Channel Value Register

§cc2_ccvp: Reg<CC2_CCVP_SPEC>

0x58 - CC Channel Value Peek Register

§cc2_ccvb: Reg<CC2_CCVB_SPEC>

0x5c - CC Channel Buffer Register

§dtctrl: Reg<DTCTRL_SPEC>

0x70 - DTI Control Register

§dttime: Reg<DTTIME_SPEC>

0x74 - DTI Time Control Register

§dtfc: Reg<DTFC_SPEC>

0x78 - DTI Fault Configuration Register

§dtogen: Reg<DTOGEN_SPEC>

0x7c - DTI Output Generation Enable Register

§dtfault: Reg<DTFAULT_SPEC>

0x80 - DTI Fault Register

§dtfaultc: Reg<DTFAULTC_SPEC>

0x84 - DTI Fault Clear Register

§dtlock: Reg<DTLOCK_SPEC>

0x88 - DTI Configuration Lock Register

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