Struct efm32gg11b_pac::efm32gg11b840::usb::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 198 fields
pub ctrl: CTRL,
pub status: STATUS,
pub if_: IF,
pub ifs: IFS,
pub ifc: IFC,
pub ien: IEN,
pub route: ROUTE,
pub cdconf: CDCONF,
pub cmd: CMD,
pub dattrim1: DATTRIM1,
pub lemctrl: LEMCTRL,
pub gotgctl: GOTGCTL,
pub gotgint: GOTGINT,
pub gahbcfg: GAHBCFG,
pub gusbcfg: GUSBCFG,
pub grstctl: GRSTCTL,
pub gintsts: GINTSTS,
pub gintmsk: GINTMSK,
pub grxstsr: GRXSTSR,
pub grxstsp: GRXSTSP,
pub grxfsiz: GRXFSIZ,
pub gnptxfsiz: GNPTXFSIZ,
pub gnptxsts: GNPTXSTS,
pub gsnpsid: GSNPSID,
pub gdfifocfg: GDFIFOCFG,
pub hptxfsiz: HPTXFSIZ,
pub dieptxf1: DIEPTXF1,
pub dieptxf2: DIEPTXF2,
pub dieptxf3: DIEPTXF3,
pub dieptxf4: DIEPTXF4,
pub dieptxf5: DIEPTXF5,
pub dieptxf6: DIEPTXF6,
pub hcfg: HCFG,
pub hfir: HFIR,
pub hfnum: HFNUM,
pub hptxsts: HPTXSTS,
pub haint: HAINT,
pub haintmsk: HAINTMSK,
pub hprt: HPRT,
pub hc0_char: HC0_CHAR,
pub hc0_splt: HC0_SPLT,
pub hc0_int: HC0_INT,
pub hc0_intmsk: HC0_INTMSK,
pub hc0_tsiz: HC0_TSIZ,
pub hc0_dmaaddr: HC0_DMAADDR,
pub hc1_char: HC1_CHAR,
pub hc1_splt: HC1_SPLT,
pub hc1_int: HC1_INT,
pub hc1_intmsk: HC1_INTMSK,
pub hc1_tsiz: HC1_TSIZ,
pub hc1_dmaaddr: HC1_DMAADDR,
pub hc2_char: HC2_CHAR,
pub hc2_splt: HC2_SPLT,
pub hc2_int: HC2_INT,
pub hc2_intmsk: HC2_INTMSK,
pub hc2_tsiz: HC2_TSIZ,
pub hc2_dmaaddr: HC2_DMAADDR,
pub hc3_char: HC3_CHAR,
pub hc3_splt: HC3_SPLT,
pub hc3_int: HC3_INT,
pub hc3_intmsk: HC3_INTMSK,
pub hc3_tsiz: HC3_TSIZ,
pub hc3_dmaaddr: HC3_DMAADDR,
pub hc4_char: HC4_CHAR,
pub hc4_splt: HC4_SPLT,
pub hc4_int: HC4_INT,
pub hc4_intmsk: HC4_INTMSK,
pub hc4_tsiz: HC4_TSIZ,
pub hc4_dmaaddr: HC4_DMAADDR,
pub hc5_char: HC5_CHAR,
pub hc5_splt: HC5_SPLT,
pub hc5_int: HC5_INT,
pub hc5_intmsk: HC5_INTMSK,
pub hc5_tsiz: HC5_TSIZ,
pub hc5_dmaaddr: HC5_DMAADDR,
pub hc6_char: HC6_CHAR,
pub hc6_splt: HC6_SPLT,
pub hc6_int: HC6_INT,
pub hc6_intmsk: HC6_INTMSK,
pub hc6_tsiz: HC6_TSIZ,
pub hc6_dmaaddr: HC6_DMAADDR,
pub hc7_char: HC7_CHAR,
pub hc7_splt: HC7_SPLT,
pub hc7_int: HC7_INT,
pub hc7_intmsk: HC7_INTMSK,
pub hc7_tsiz: HC7_TSIZ,
pub hc7_dmaaddr: HC7_DMAADDR,
pub hc8_char: HC8_CHAR,
pub hc8_splt: HC8_SPLT,
pub hc8_int: HC8_INT,
pub hc8_intmsk: HC8_INTMSK,
pub hc8_tsiz: HC8_TSIZ,
pub hc8_dmaaddr: HC8_DMAADDR,
pub hc9_char: HC9_CHAR,
pub hc9_splt: HC9_SPLT,
pub hc9_int: HC9_INT,
pub hc9_intmsk: HC9_INTMSK,
pub hc9_tsiz: HC9_TSIZ,
pub hc9_dmaaddr: HC9_DMAADDR,
pub hc10_char: HC10_CHAR,
pub hc10_splt: HC10_SPLT,
pub hc10_int: HC10_INT,
pub hc10_intmsk: HC10_INTMSK,
pub hc10_tsiz: HC10_TSIZ,
pub hc10_dmaaddr: HC10_DMAADDR,
pub hc11_char: HC11_CHAR,
pub hc11_splt: HC11_SPLT,
pub hc11_int: HC11_INT,
pub hc11_intmsk: HC11_INTMSK,
pub hc11_tsiz: HC11_TSIZ,
pub hc11_dmaaddr: HC11_DMAADDR,
pub hc12_char: HC12_CHAR,
pub hc12_splt: HC12_SPLT,
pub hc12_int: HC12_INT,
pub hc12_intmsk: HC12_INTMSK,
pub hc12_tsiz: HC12_TSIZ,
pub hc12_dmaaddr: HC12_DMAADDR,
pub hc13_char: HC13_CHAR,
pub hc13_splt: HC13_SPLT,
pub hc13_int: HC13_INT,
pub hc13_intmsk: HC13_INTMSK,
pub hc13_tsiz: HC13_TSIZ,
pub hc13_dmaaddr: HC13_DMAADDR,
pub dcfg: DCFG,
pub dctl: DCTL,
pub dsts: DSTS,
pub diepmsk: DIEPMSK,
pub doepmsk: DOEPMSK,
pub daint: DAINT,
pub daintmsk: DAINTMSK,
pub dvbusdis: DVBUSDIS,
pub dvbuspulse: DVBUSPULSE,
pub dthrctl: DTHRCTL,
pub diepempmsk: DIEPEMPMSK,
pub diep0ctl: DIEP0CTL,
pub diep0int: DIEP0INT,
pub diep0tsiz: DIEP0TSIZ,
pub diep0dmaaddr: DIEP0DMAADDR,
pub diep0txfsts: DIEP0TXFSTS,
pub diep0_ctl: DIEP0_CTL,
pub diep0_int: DIEP0_INT,
pub diep0_tsiz: DIEP0_TSIZ,
pub diep0_dmaaddr: DIEP0_DMAADDR,
pub diep0_dtxfsts: DIEP0_DTXFSTS,
pub diep1_ctl: DIEP1_CTL,
pub diep1_int: DIEP1_INT,
pub diep1_tsiz: DIEP1_TSIZ,
pub diep1_dmaaddr: DIEP1_DMAADDR,
pub diep1_dtxfsts: DIEP1_DTXFSTS,
pub diep2_ctl: DIEP2_CTL,
pub diep2_int: DIEP2_INT,
pub diep2_tsiz: DIEP2_TSIZ,
pub diep2_dmaaddr: DIEP2_DMAADDR,
pub diep2_dtxfsts: DIEP2_DTXFSTS,
pub diep3_ctl: DIEP3_CTL,
pub diep3_int: DIEP3_INT,
pub diep3_tsiz: DIEP3_TSIZ,
pub diep3_dmaaddr: DIEP3_DMAADDR,
pub diep3_dtxfsts: DIEP3_DTXFSTS,
pub diep4_ctl: DIEP4_CTL,
pub diep4_int: DIEP4_INT,
pub diep4_tsiz: DIEP4_TSIZ,
pub diep4_dmaaddr: DIEP4_DMAADDR,
pub diep4_dtxfsts: DIEP4_DTXFSTS,
pub diep5_ctl: DIEP5_CTL,
pub diep5_int: DIEP5_INT,
pub diep5_tsiz: DIEP5_TSIZ,
pub diep5_dmaaddr: DIEP5_DMAADDR,
pub diep5_dtxfsts: DIEP5_DTXFSTS,
pub doep0ctl: DOEP0CTL,
pub doep0int: DOEP0INT,
pub doep0tsiz: DOEP0TSIZ,
pub doep0dmaaddr: DOEP0DMAADDR,
pub doep0_ctl: DOEP0_CTL,
pub doep0_int: DOEP0_INT,
pub doep0_tsiz: DOEP0_TSIZ,
pub doep0_dmaaddr: DOEP0_DMAADDR,
pub doep1_ctl: DOEP1_CTL,
pub doep1_int: DOEP1_INT,
pub doep1_tsiz: DOEP1_TSIZ,
pub doep1_dmaaddr: DOEP1_DMAADDR,
pub doep2_ctl: DOEP2_CTL,
pub doep2_int: DOEP2_INT,
pub doep2_tsiz: DOEP2_TSIZ,
pub doep2_dmaaddr: DOEP2_DMAADDR,
pub doep3_ctl: DOEP3_CTL,
pub doep3_int: DOEP3_INT,
pub doep3_tsiz: DOEP3_TSIZ,
pub doep3_dmaaddr: DOEP3_DMAADDR,
pub doep4_ctl: DOEP4_CTL,
pub doep4_int: DOEP4_INT,
pub doep4_tsiz: DOEP4_TSIZ,
pub doep4_dmaaddr: DOEP4_DMAADDR,
pub doep5_ctl: DOEP5_CTL,
pub doep5_int: DOEP5_INT,
pub doep5_tsiz: DOEP5_TSIZ,
pub doep5_dmaaddr: DOEP5_DMAADDR,
pub pcgcctl: PCGCCTL,
/* private fields */
}
Expand description
Register block
Fields§
§ctrl: CTRL
0x00 - System Control Register
status: STATUS
0x04 - System Status Register
if_: IF
0x08 - Interrupt Flag Register
ifs: IFS
0x0c - Interrupt Flag Set Register
ifc: IFC
0x10 - Interrupt Flag Clear Register
ien: IEN
0x14 - Interrupt Enable Register
route: ROUTE
0x18 - I/O Routing Register
cdconf: CDCONF
0x2c - Charger Detect Configuration Register
cmd: CMD
0x30 - Command Register
dattrim1: DATTRIM1
0x34 - Data TRIM 1 Values for USB DP and DM
lemctrl: LEMCTRL
0x3c - USB LEM Control Register
gotgctl: GOTGCTL
0xde000 - OTG Control and Status Register
gotgint: GOTGINT
0xde004 - OTG Interrupt Register
gahbcfg: GAHBCFG
0xde008 - AHB Configuration Register
gusbcfg: GUSBCFG
0xde00c - USB Configuration Register
grstctl: GRSTCTL
0xde010 - Reset Register
gintsts: GINTSTS
0xde014 - Interrupt Register
gintmsk: GINTMSK
0xde018 - Interrupt Mask Register
grxstsr: GRXSTSR
0xde01c - Receive Status Debug Read Register
grxstsp: GRXSTSP
0xde020 - Receive Status Read /Pop Register
grxfsiz: GRXFSIZ
0xde024 - Receive FIFO Size Register
gnptxfsiz: GNPTXFSIZ
0xde028 - Non-periodic Transmit FIFO Size Register
gnptxsts: GNPTXSTS
0xde02c - Non-periodic Transmit FIFO/Queue Status Register
gsnpsid: GSNPSID
0xde040 - Synopsys ID Register
gdfifocfg: GDFIFOCFG
0xde05c - Global DFIFO Configuration Register
hptxfsiz: HPTXFSIZ
0xde100 - Host Periodic Transmit FIFO Size Register
dieptxf1: DIEPTXF1
0xde104 - Device IN Endpoint Transmit FIFO Size Register 1
dieptxf2: DIEPTXF2
0xde108 - Device IN Endpoint Transmit FIFO Size Register 2
dieptxf3: DIEPTXF3
0xde10c - Device IN Endpoint Transmit FIFO Size Register 3
dieptxf4: DIEPTXF4
0xde110 - Device IN Endpoint Transmit FIFO Size Register 4
dieptxf5: DIEPTXF5
0xde114 - Device IN Endpoint Transmit FIFO Size Register 5
dieptxf6: DIEPTXF6
0xde118 - Device IN Endpoint Transmit FIFO Size Register 6
hcfg: HCFG
0xde400 - Host Configuration Register
hfir: HFIR
0xde404 - Host Frame Interval Register
hfnum: HFNUM
0xde408 - Host Frame Number/Frame Time Remaining Register
hptxsts: HPTXSTS
0xde410 - Host Periodic Transmit FIFO/Queue Status Register
haint: HAINT
0xde414 - Host All Channels Interrupt Register
haintmsk: HAINTMSK
0xde418 - Host All Channels Interrupt Mask Register
hprt: HPRT
0xde440 - Host Port Control and Status Register
hc0_char: HC0_CHAR
0xde500 - Host Channel x Characteristics Register
hc0_splt: HC0_SPLT
0xde504 - Host Channel x Split Control Register
hc0_int: HC0_INT
0xde508 - Host Channel x Interrupt Register
hc0_intmsk: HC0_INTMSK
0xde50c - Host Channel x Interrupt Mask Register
hc0_tsiz: HC0_TSIZ
0xde510 - Host Channel x Transfer Size Register
hc0_dmaaddr: HC0_DMAADDR
0xde514 - Host Channel x DMA Address Register
hc1_char: HC1_CHAR
0xde520 - Host Channel x Characteristics Register
hc1_splt: HC1_SPLT
0xde524 - Host Channel x Split Control Register
hc1_int: HC1_INT
0xde528 - Host Channel x Interrupt Register
hc1_intmsk: HC1_INTMSK
0xde52c - Host Channel x Interrupt Mask Register
hc1_tsiz: HC1_TSIZ
0xde530 - Host Channel x Transfer Size Register
hc1_dmaaddr: HC1_DMAADDR
0xde534 - Host Channel x DMA Address Register
hc2_char: HC2_CHAR
0xde540 - Host Channel x Characteristics Register
hc2_splt: HC2_SPLT
0xde544 - Host Channel x Split Control Register
hc2_int: HC2_INT
0xde548 - Host Channel x Interrupt Register
hc2_intmsk: HC2_INTMSK
0xde54c - Host Channel x Interrupt Mask Register
hc2_tsiz: HC2_TSIZ
0xde550 - Host Channel x Transfer Size Register
hc2_dmaaddr: HC2_DMAADDR
0xde554 - Host Channel x DMA Address Register
hc3_char: HC3_CHAR
0xde560 - Host Channel x Characteristics Register
hc3_splt: HC3_SPLT
0xde564 - Host Channel x Split Control Register
hc3_int: HC3_INT
0xde568 - Host Channel x Interrupt Register
hc3_intmsk: HC3_INTMSK
0xde56c - Host Channel x Interrupt Mask Register
hc3_tsiz: HC3_TSIZ
0xde570 - Host Channel x Transfer Size Register
hc3_dmaaddr: HC3_DMAADDR
0xde574 - Host Channel x DMA Address Register
hc4_char: HC4_CHAR
0xde580 - Host Channel x Characteristics Register
hc4_splt: HC4_SPLT
0xde584 - Host Channel x Split Control Register
hc4_int: HC4_INT
0xde588 - Host Channel x Interrupt Register
hc4_intmsk: HC4_INTMSK
0xde58c - Host Channel x Interrupt Mask Register
hc4_tsiz: HC4_TSIZ
0xde590 - Host Channel x Transfer Size Register
hc4_dmaaddr: HC4_DMAADDR
0xde594 - Host Channel x DMA Address Register
hc5_char: HC5_CHAR
0xde5a0 - Host Channel x Characteristics Register
hc5_splt: HC5_SPLT
0xde5a4 - Host Channel x Split Control Register
hc5_int: HC5_INT
0xde5a8 - Host Channel x Interrupt Register
hc5_intmsk: HC5_INTMSK
0xde5ac - Host Channel x Interrupt Mask Register
hc5_tsiz: HC5_TSIZ
0xde5b0 - Host Channel x Transfer Size Register
hc5_dmaaddr: HC5_DMAADDR
0xde5b4 - Host Channel x DMA Address Register
hc6_char: HC6_CHAR
0xde5c0 - Host Channel x Characteristics Register
hc6_splt: HC6_SPLT
0xde5c4 - Host Channel x Split Control Register
hc6_int: HC6_INT
0xde5c8 - Host Channel x Interrupt Register
hc6_intmsk: HC6_INTMSK
0xde5cc - Host Channel x Interrupt Mask Register
hc6_tsiz: HC6_TSIZ
0xde5d0 - Host Channel x Transfer Size Register
hc6_dmaaddr: HC6_DMAADDR
0xde5d4 - Host Channel x DMA Address Register
hc7_char: HC7_CHAR
0xde5e0 - Host Channel x Characteristics Register
hc7_splt: HC7_SPLT
0xde5e4 - Host Channel x Split Control Register
hc7_int: HC7_INT
0xde5e8 - Host Channel x Interrupt Register
hc7_intmsk: HC7_INTMSK
0xde5ec - Host Channel x Interrupt Mask Register
hc7_tsiz: HC7_TSIZ
0xde5f0 - Host Channel x Transfer Size Register
hc7_dmaaddr: HC7_DMAADDR
0xde5f4 - Host Channel x DMA Address Register
hc8_char: HC8_CHAR
0xde600 - Host Channel x Characteristics Register
hc8_splt: HC8_SPLT
0xde604 - Host Channel x Split Control Register
hc8_int: HC8_INT
0xde608 - Host Channel x Interrupt Register
hc8_intmsk: HC8_INTMSK
0xde60c - Host Channel x Interrupt Mask Register
hc8_tsiz: HC8_TSIZ
0xde610 - Host Channel x Transfer Size Register
hc8_dmaaddr: HC8_DMAADDR
0xde614 - Host Channel x DMA Address Register
hc9_char: HC9_CHAR
0xde620 - Host Channel x Characteristics Register
hc9_splt: HC9_SPLT
0xde624 - Host Channel x Split Control Register
hc9_int: HC9_INT
0xde628 - Host Channel x Interrupt Register
hc9_intmsk: HC9_INTMSK
0xde62c - Host Channel x Interrupt Mask Register
hc9_tsiz: HC9_TSIZ
0xde630 - Host Channel x Transfer Size Register
hc9_dmaaddr: HC9_DMAADDR
0xde634 - Host Channel x DMA Address Register
hc10_char: HC10_CHAR
0xde640 - Host Channel x Characteristics Register
hc10_splt: HC10_SPLT
0xde644 - Host Channel x Split Control Register
hc10_int: HC10_INT
0xde648 - Host Channel x Interrupt Register
hc10_intmsk: HC10_INTMSK
0xde64c - Host Channel x Interrupt Mask Register
hc10_tsiz: HC10_TSIZ
0xde650 - Host Channel x Transfer Size Register
hc10_dmaaddr: HC10_DMAADDR
0xde654 - Host Channel x DMA Address Register
hc11_char: HC11_CHAR
0xde660 - Host Channel x Characteristics Register
hc11_splt: HC11_SPLT
0xde664 - Host Channel x Split Control Register
hc11_int: HC11_INT
0xde668 - Host Channel x Interrupt Register
hc11_intmsk: HC11_INTMSK
0xde66c - Host Channel x Interrupt Mask Register
hc11_tsiz: HC11_TSIZ
0xde670 - Host Channel x Transfer Size Register
hc11_dmaaddr: HC11_DMAADDR
0xde674 - Host Channel x DMA Address Register
hc12_char: HC12_CHAR
0xde680 - Host Channel x Characteristics Register
hc12_splt: HC12_SPLT
0xde684 - Host Channel x Split Control Register
hc12_int: HC12_INT
0xde688 - Host Channel x Interrupt Register
hc12_intmsk: HC12_INTMSK
0xde68c - Host Channel x Interrupt Mask Register
hc12_tsiz: HC12_TSIZ
0xde690 - Host Channel x Transfer Size Register
hc12_dmaaddr: HC12_DMAADDR
0xde694 - Host Channel x DMA Address Register
hc13_char: HC13_CHAR
0xde6a0 - Host Channel x Characteristics Register
hc13_splt: HC13_SPLT
0xde6a4 - Host Channel x Split Control Register
hc13_int: HC13_INT
0xde6a8 - Host Channel x Interrupt Register
hc13_intmsk: HC13_INTMSK
0xde6ac - Host Channel x Interrupt Mask Register
hc13_tsiz: HC13_TSIZ
0xde6b0 - Host Channel x Transfer Size Register
hc13_dmaaddr: HC13_DMAADDR
0xde6b4 - Host Channel x DMA Address Register
dcfg: DCFG
0xde800 - Device Configuration Register
dctl: DCTL
0xde804 - Device Control Register
dsts: DSTS
0xde808 - Device Status Register
diepmsk: DIEPMSK
0xde810 - Device IN Endpoint Common Interrupt Mask Register
doepmsk: DOEPMSK
0xde814 - Device OUT Endpoint Common Interrupt Mask Register
daint: DAINT
0xde818 - Device All Endpoints Interrupt Register
daintmsk: DAINTMSK
0xde81c - Device All Endpoints Interrupt Mask Register
dvbusdis: DVBUSDIS
0xde828 - Device VBUS Discharge Time Register
dvbuspulse: DVBUSPULSE
0xde82c - Device VBUS Pulsing Time Register
dthrctl: DTHRCTL
0xde830 - Device Threshold Control Register
diepempmsk: DIEPEMPMSK
0xde834 - Device IN Endpoint FIFO Empty Interrupt Mask Register
diep0ctl: DIEP0CTL
0xde900 - Device Control IN Endpoint 0 Control Register
diep0int: DIEP0INT
0xde908 - Device IN Endpoint 0 Interrupt Register
diep0tsiz: DIEP0TSIZ
0xde910 - Device IN Endpoint 0 Transfer Size Register
diep0dmaaddr: DIEP0DMAADDR
0xde914 - Device IN Endpoint 0 DMA Address Register
diep0txfsts: DIEP0TXFSTS
0xde918 - Device IN Endpoint Transmit FIFO Status Register 0
diep0_ctl: DIEP0_CTL
0xde920 - Device Control IN Endpoint x+1 Control Register
diep0_int: DIEP0_INT
0xde928 - Device IN Endpoint x+1 Interrupt Register
diep0_tsiz: DIEP0_TSIZ
0xde930 - Device IN Endpoint x+1 Transfer Size Register
diep0_dmaaddr: DIEP0_DMAADDR
0xde934 - Device IN Endpoint x+1 DMA Address Register
diep0_dtxfsts: DIEP0_DTXFSTS
0xde938 - Device IN Endpoint Transmit FIFO Status Register 1
diep1_ctl: DIEP1_CTL
0xde940 - Device Control IN Endpoint x+1 Control Register
diep1_int: DIEP1_INT
0xde948 - Device IN Endpoint x+1 Interrupt Register
diep1_tsiz: DIEP1_TSIZ
0xde950 - Device IN Endpoint x+1 Transfer Size Register
diep1_dmaaddr: DIEP1_DMAADDR
0xde954 - Device IN Endpoint x+1 DMA Address Register
diep1_dtxfsts: DIEP1_DTXFSTS
0xde958 - Device IN Endpoint Transmit FIFO Status Register 1
diep2_ctl: DIEP2_CTL
0xde960 - Device Control IN Endpoint x+1 Control Register
diep2_int: DIEP2_INT
0xde968 - Device IN Endpoint x+1 Interrupt Register
diep2_tsiz: DIEP2_TSIZ
0xde970 - Device IN Endpoint x+1 Transfer Size Register
diep2_dmaaddr: DIEP2_DMAADDR
0xde974 - Device IN Endpoint x+1 DMA Address Register
diep2_dtxfsts: DIEP2_DTXFSTS
0xde978 - Device IN Endpoint Transmit FIFO Status Register 1
diep3_ctl: DIEP3_CTL
0xde980 - Device Control IN Endpoint x+1 Control Register
diep3_int: DIEP3_INT
0xde988 - Device IN Endpoint x+1 Interrupt Register
diep3_tsiz: DIEP3_TSIZ
0xde990 - Device IN Endpoint x+1 Transfer Size Register
diep3_dmaaddr: DIEP3_DMAADDR
0xde994 - Device IN Endpoint x+1 DMA Address Register
diep3_dtxfsts: DIEP3_DTXFSTS
0xde998 - Device IN Endpoint Transmit FIFO Status Register 1
diep4_ctl: DIEP4_CTL
0xde9a0 - Device Control IN Endpoint x+1 Control Register
diep4_int: DIEP4_INT
0xde9a8 - Device IN Endpoint x+1 Interrupt Register
diep4_tsiz: DIEP4_TSIZ
0xde9b0 - Device IN Endpoint x+1 Transfer Size Register
diep4_dmaaddr: DIEP4_DMAADDR
0xde9b4 - Device IN Endpoint x+1 DMA Address Register
diep4_dtxfsts: DIEP4_DTXFSTS
0xde9b8 - Device IN Endpoint Transmit FIFO Status Register 1
diep5_ctl: DIEP5_CTL
0xde9c0 - Device Control IN Endpoint x+1 Control Register
diep5_int: DIEP5_INT
0xde9c8 - Device IN Endpoint x+1 Interrupt Register
diep5_tsiz: DIEP5_TSIZ
0xde9d0 - Device IN Endpoint x+1 Transfer Size Register
diep5_dmaaddr: DIEP5_DMAADDR
0xde9d4 - Device IN Endpoint x+1 DMA Address Register
diep5_dtxfsts: DIEP5_DTXFSTS
0xde9d8 - Device IN Endpoint Transmit FIFO Status Register 1
doep0ctl: DOEP0CTL
0xdeb00 - Device Control OUT Endpoint 0 Control Register
doep0int: DOEP0INT
0xdeb08 - Device OUT Endpoint 0 Interrupt Register
doep0tsiz: DOEP0TSIZ
0xdeb10 - Device OUT Endpoint 0 Transfer Size Register
doep0dmaaddr: DOEP0DMAADDR
0xdeb14 - Device OUT Endpoint 0 DMA Address Register
doep0_ctl: DOEP0_CTL
0xdeb20 - Device Control OUT Endpoint x+1 Control Register
doep0_int: DOEP0_INT
0xdeb28 - Device OUT Endpoint x+1 Interrupt Register
doep0_tsiz: DOEP0_TSIZ
0xdeb30 - Device OUT Endpoint x+1 Transfer Size Register
doep0_dmaaddr: DOEP0_DMAADDR
0xdeb34 - Device OUT Endpoint x+1 DMA Address Register
doep1_ctl: DOEP1_CTL
0xdeb40 - Device Control OUT Endpoint x+1 Control Register
doep1_int: DOEP1_INT
0xdeb48 - Device OUT Endpoint x+1 Interrupt Register
doep1_tsiz: DOEP1_TSIZ
0xdeb50 - Device OUT Endpoint x+1 Transfer Size Register
doep1_dmaaddr: DOEP1_DMAADDR
0xdeb54 - Device OUT Endpoint x+1 DMA Address Register
doep2_ctl: DOEP2_CTL
0xdeb60 - Device Control OUT Endpoint x+1 Control Register
doep2_int: DOEP2_INT
0xdeb68 - Device OUT Endpoint x+1 Interrupt Register
doep2_tsiz: DOEP2_TSIZ
0xdeb70 - Device OUT Endpoint x+1 Transfer Size Register
doep2_dmaaddr: DOEP2_DMAADDR
0xdeb74 - Device OUT Endpoint x+1 DMA Address Register
doep3_ctl: DOEP3_CTL
0xdeb80 - Device Control OUT Endpoint x+1 Control Register
doep3_int: DOEP3_INT
0xdeb88 - Device OUT Endpoint x+1 Interrupt Register
doep3_tsiz: DOEP3_TSIZ
0xdeb90 - Device OUT Endpoint x+1 Transfer Size Register
doep3_dmaaddr: DOEP3_DMAADDR
0xdeb94 - Device OUT Endpoint x+1 DMA Address Register
doep4_ctl: DOEP4_CTL
0xdeba0 - Device Control OUT Endpoint x+1 Control Register
doep4_int: DOEP4_INT
0xdeba8 - Device OUT Endpoint x+1 Interrupt Register
doep4_tsiz: DOEP4_TSIZ
0xdebb0 - Device OUT Endpoint x+1 Transfer Size Register
doep4_dmaaddr: DOEP4_DMAADDR
0xdebb4 - Device OUT Endpoint x+1 DMA Address Register
doep5_ctl: DOEP5_CTL
0xdebc0 - Device Control OUT Endpoint x+1 Control Register
doep5_int: DOEP5_INT
0xdebc8 - Device OUT Endpoint x+1 Interrupt Register
doep5_tsiz: DOEP5_TSIZ
0xdebd0 - Device OUT Endpoint x+1 Transfer Size Register
doep5_dmaaddr: DOEP5_DMAADDR
0xdebd4 - Device OUT Endpoint x+1 DMA Address Register
pcgcctl: PCGCCTL
0xdee00 - Power and Clock Gating Control Register