Type Definition efm32gg11b_pac::efm32gg11b110::msc::cacheconfig0::CACHELPLEVEL_W

pub type CACHELPLEVEL_W<'a, const O: u8> = FieldWriter<'a, u32, CACHECONFIG0_SPEC, u8, CACHELPLEVEL_A, 2, O>;

Field CACHELPLEVEL writer - Instruction Cache Low-Power Level

Implementations

impl<'a, const O: u8> CACHELPLEVEL_W<'a, O>

pub fn base(self) -> &'a mut W

Base instruction cache functionality.

pub fn advanced(self) -> &'a mut W

Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory.

pub fn minactivity(self) -> &'a mut W

Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality.