pub struct DW3000<SPI, CS> { /* private fields */ }
Expand description

Entry point to the DW3000 driver’s low-level API

Please consider using hl::DW3000 instead.

Implementations

Create a new instance of DW3000

Requires the SPI peripheral and the chip select pin that are connected to the DW3000.

commentaire

Device identifier

Extended Unique Identifier

PAN Identifier and Short Address

System Configuration

comments

SPI CRC read status

System Time Counter register

TX Frame Control

Delayed Send or Receive Time

Delayed send or receive reference time

Receive frame wait timeout period

System Control Register

System event enable mask register

System Event Status Register

RX Frame Information

Receive Time Stamp

Transmit Time Stamp

Transmit time stamp raw

Transmitter antenna delay

Acknowledgement delay time and response time

TX Power Control

Channel Control Register

Low Energy device address 0 and 1

Low Energy device address 2 and 3

SPI collision status

RX double buffer status

RX double buffer diagnostic configuration

AES configuration

AES GCM core mode

AES GCM core mode

AES GCM core mode

AES GCM core mode

AES GCM core mode

DMA configuration register

Start AES operation

The AES Status

The 128-bit KEY for the AES GCM/CCM* core

STS configuration

STS control

STS status

STS 128-bit KEY

STS 128-bit IV

RX tuning configuration register

DGC_CFG0

DGC_CFG1

DGC_LUT_0

DGC_LUT_1

DGC_LUT_2

DGC_LUT_3

DGC_LUT_4

DGC_LUT_5

DGC_LUT_6

Reports DGC information

External clock synchronisation counter configuration

RX calibration block configuration

RX calibration block result

RX calibration block result

RX calibration block status

GPIO Mode Control Register

GPIO Drive Strength and Pull Control

GPIO Direction Control Register

GPIO Data Output Register

GPIO Interrupt Enable

GPIO Interrupt Status

GPIO Interrupt Sense Selection

GPIO Interrupt Mode (Level / Edge)

GPIO Interrupt “Both Edge” Select

GPIO Interrupt Latch Clear

GPIO Interrupt De-bounce Enable

GPIO Raw State

PAC configuration

SFD timeout

Preamble detection timeout

Receiver tuning register

Digital Tuning Reserved register

Carrier recovery integrator register

RF control enable

RF enable mask

RF switch configuration

RF transmitter configuration

RF transmitter configuration

Transmitter test configuration

Transmitter Calibration – SAR temperaturesensor read enable

Internal LDO voltage tuning parameter

LDO control

LDO tuning register

Transmitter Calibration – SAR control

Transmitter Calibration – SAR status

Transmitter Calibration –Latest SAR readings

Transmitter Calibration – SAR readings at last wake-up

Transmitter Calibration – Pulse Generator control

Transmitter Calibration – Pulse Generator status

Transmitter Calibration – Pulse Generator test

Transmitter Calibration – Pulse Generator count target value

PLL configuration

PLL coarse code – starting code for calibration procedure

PLL calibration configuration

Frequency synthesiser – Crystal trim

AON wake up configuration register

AON control register

AON direct access read data result

AON direct access address

AON direct access write data

AON configuration register

OTP data to program to a particular address

OTP address to which to program the data

OTP configuration register

OTP memory programming status register

OTP data read from given address

OTP Special Register (SR) read data

Preamble sequence receive time stamp and status

STS receive time stamp and status

2nd STS receive time stamp and status

The TDoA between the two CIRs

The PDoA between the two CIRs

CIA Diagnostic 0

Reserved diagnostic data

Preamble Diagnostic 0 – peak

Preamble Diagnostic 1 – power indication

Preamble Diagnostic 2 – magnitude @ FP + 1

Preamble Diagnostic 3 – magnitude @ FP + 2

Preamble Diagnostic 4 – magnitude @ FP + 3

Reserved diagnostic data

Preamble Diagnostic 8 – first path

Reserved diagnostic data

Preamble Diagnostic 12 – symbols accumulated

STS 0 Diagnostic 0 – STS CIA peak amplitude

STS 0 Diagnostic 1 – STS power indication

STS 0 Diagnostic 2 – STS magnitude @ FP + 1

STS 0 Diagnostic 3 – STS magnitude @ FP + 2

STS 0 Diagnostic 4 – STS magnitude @ FP + 3

Reserved diagnostic data

STS 0 Diagnostic 8 – STS first path

Reserved diagnostic data

STS 0 diagnostic 12 – accumulated STS length

Reserved diagnostic data

STS 1 Diagnostic 0 – STS CIA peak amplitude

STS 1 Diagnostic 1 – STS power indication

STS 1 Diagnostic 2 – STS magnitude @ FP + 1

STS 1 Diagnostic 3 – STS magnitude @ FP + 2

STS 1 Diagnostic 4 – STS magnitude @ FP + 3

Reserved diagnostic data

STS 1 Diagnostic 8 – STS first path

Reserved diagnostic data

STS 1 Diagnostic 12 – STS accumulated STS length

CIA general configuration

First path temp adjustment and thresholds

Preamble Config – CIA preamble configuration

STS Config 0 – CIA STS configuration

STS Config 1 – CIA STS configuration

User adjustment to the PDoA

Event counter control

PHR error counter

RSD error counter

Frame check sequence good counter

Frame Check Sequence error counter

Frame filter rejection counter

RX overrun error counter

SFD timeout counter

Preamble timeout counter

RX frame wait timeout counter

TX frame sent counter

Half period warning counter

SPI write CRC error counter

Digital diagnostics reserved area 1

Test mode control register

STS quality error counter

Low voltage warning error counter

SPI mode

System states *

Fast command status

Current value of the low 32-bits of the STS IV

SPI CRC LFSR initialisation code

Soft reset of the device blocks

PMSC clock control register

PMSC sequencing control register

PMSC fine grain TX sequencing control

PMSC fine grain TX sequencing control

Receiver SNIFF mode configuration

Analog blocks’ calibration values

Read access to accumulator data memory

Scratch RAM memory buffer

storage for up to 8 x 128 bit AES KEYs

Double buffer diagnostic register set

Double buffer diagnostic register set 1

Double buffer diagnostic register set 2

Indirect pointer A

Indirect pointer B

Fast System Event Status Register

Base address of the register to be accessed through indirect pointer A

Offset address of the register to be accessed through indirect pointer A

Base address of the register to be accessed through indirect pointer B

Offset address of the register to be accessed through indirect pointer B

Transmit Data Buffer

Receive Data Buffer

Receive Data Buffer1

Trait Implementations

Returns a copy of the value. Read more

Performs copy-assignment from source. Read more

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