Enum ParallelAlu 

pub enum ParallelAlu {
    Move,
    TfrAcc {
        src: Accumulator,
        d: Accumulator,
    },
    Addr {
        src: Accumulator,
        d: Accumulator,
    },
    Tst {
        d: Accumulator,
    },
    CmpAcc {
        src: Accumulator,
        d: Accumulator,
    },
    Subr {
        src: Accumulator,
        d: Accumulator,
    },
    CmpmAcc {
        src: Accumulator,
        d: Accumulator,
    },
    AddAcc {
        src: Accumulator,
        d: Accumulator,
    },
    Rnd {
        d: Accumulator,
    },
    Addl {
        src: Accumulator,
        d: Accumulator,
    },
    Clr {
        d: Accumulator,
    },
    SubAcc {
        src: Accumulator,
        d: Accumulator,
    },
    Max,
    Maxm,
    Subl {
        src: Accumulator,
        d: Accumulator,
    },
    Not {
        d: Accumulator,
    },
    AddXY {
        hi: usize,
        lo: usize,
        d: Accumulator,
    },
    Adc {
        hi: usize,
        lo: usize,
        d: Accumulator,
    },
    SubXY {
        hi: usize,
        lo: usize,
        d: Accumulator,
    },
    Sbc {
        hi: usize,
        lo: usize,
        d: Accumulator,
    },
    Asr {
        d: Accumulator,
    },
    Lsr {
        d: Accumulator,
    },
    Abs {
        d: Accumulator,
    },
    Ror {
        d: Accumulator,
    },
    Asl {
        d: Accumulator,
    },
    Lsl {
        d: Accumulator,
    },
    Neg {
        d: Accumulator,
    },
    Rol {
        d: Accumulator,
    },
    AddReg {
        src: usize,
        d: Accumulator,
    },
    TfrReg {
        src: usize,
        d: Accumulator,
    },
    Or {
        src: usize,
        d: Accumulator,
    },
    Eor {
        src: usize,
        d: Accumulator,
    },
    SubReg {
        src: usize,
        d: Accumulator,
    },
    CmpReg {
        src: usize,
        d: Accumulator,
    },
    And {
        src: usize,
        d: Accumulator,
    },
    CmpmReg {
        src: usize,
        d: Accumulator,
    },
    Mpy {
        negate: bool,
        s1: usize,
        s2: usize,
        d: Accumulator,
    },
    Mpyr {
        negate: bool,
        s1: usize,
        s2: usize,
        d: Accumulator,
    },
    Mac {
        negate: bool,
        s1: usize,
        s2: usize,
        d: Accumulator,
    },
    Macr {
        negate: bool,
        s1: usize,
        s2: usize,
        d: Accumulator,
    },
    Undefined,
}

Decoded parallel ALU operation (bits 7:0 of a parallel instruction).

The encoding is defined in DSP56300FM Tables 12-19 and 12-20:

• Non-multiply (0x00-0x7F): 0 JJJ D kkk
• Multiply (0x80-0xFF): 1 QQQ d kkk

Variants

Move

0x00: No ALU operation (move-only parallel)

TfrAcc

Fields

src: Accumulator

d: Accumulator

Addr

Fields

src: Accumulator

d: Accumulator

Tst

Fields

d: Accumulator

CmpAcc

Fields

src: Accumulator

d: Accumulator

Subr

Fields

src: Accumulator

d: Accumulator

CmpmAcc

Fields

src: Accumulator

d: Accumulator

AddAcc

Fields

src: Accumulator

d: Accumulator

Rnd

Fields

d: Accumulator

Addl

Fields

src: Accumulator

d: Accumulator

Clr

Fields

d: Accumulator

SubAcc

Fields

src: Accumulator

d: Accumulator

Max

0x1D: always max a,b

Maxm

0x15: always maxm a,b

Subl

Fields

src: Accumulator

d: Accumulator

Not

Fields

d: Accumulator

AddXY

Fields

hi: usize

lo: usize

d: Accumulator

Adc

Fields

hi: usize

lo: usize

d: Accumulator

SubXY

Fields

hi: usize

lo: usize

d: Accumulator

Sbc

Fields

hi: usize

lo: usize

d: Accumulator

Asr

Fields

d: Accumulator

Lsr

Fields

d: Accumulator

Abs

Fields

d: Accumulator

Ror

Fields

d: Accumulator

Asl

Fields

d: Accumulator

Lsl

Fields

d: Accumulator

Neg

Fields

d: Accumulator

Rol

Fields

d: Accumulator

AddReg

Fields

src: usize

d: Accumulator

TfrReg

Fields

src: usize

d: Accumulator

Or

Fields

src: usize

d: Accumulator

Eor

Fields

src: usize

d: Accumulator

SubReg

Fields

src: usize

d: Accumulator

CmpReg

Fields

src: usize

d: Accumulator

And

Fields

src: usize

d: Accumulator

CmpmReg

Fields

src: usize

d: Accumulator

Mpy

Fields

negate: bool

s1: usize

s2: usize

d: Accumulator

Mpyr

Fields

negate: bool

s1: usize

s2: usize

d: Accumulator

Mac

Fields

negate: bool

s1: usize

s2: usize

d: Accumulator

Macr

Fields

negate: bool

s1: usize

s2: usize

d: Accumulator

Undefined

Undefined encoding (0x04, 0x08, 0x0C, 0x15)

Implementations

impl ParallelAlu

pub fn encode(&self) -> Option<u8>

Encode back to the ALU byte. Returns None for Undefined.

pub fn dest_accumulator(&self) -> Option<Accumulator>

The destination accumulator of this ALU operation, if any. Returns None for Move, Undefined, and comparison/test ops (Cmp*, Cmpm*, Tst).

pub fn from_text(text: &str) -> Option<ParallelAlu>

Parse from the display text format (inverse of Display).

Accepts strings like "add x,a", "mpy +x0,y1,b", "move", etc.

pub fn is_logical_or_shift(&self) -> bool

Whether this is a logical or shift operation (writes only A1/B1, not full accumulator).

Trait Implementations

impl Clone for ParallelAlu

fn clone(&self) -> ParallelAlu

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for ParallelAlu

impl Debug for ParallelAlu

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Display for ParallelAlu

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for ParallelAlu

impl PartialEq for ParallelAlu

fn eq(&self, other: &ParallelAlu) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for ParallelAlu