Struct drv2605::Control2Reg

pub struct Control2Reg(pub u8);

Methods

impl Control2Reg

pub fn bidir_input(&self) -> bool

The BIDIR_INPUT bit selects how the engine interprets data. 0: Unidirectional input mode Braking is automatically determined by the feedback conditions and is applied when needed. Use of this mode also recovers an additional bit of vertical resolution. This mode should only be used for closed-loop operation. Examples:: 0% Input -> No output signal 50% Input -> Half-scale output signal 100% Input -> Full-scale output signal 1: Bidirectional input mode (default) This mode is compatible with traditional open-loop signaling and also works well with closed-loop mode. When operating closed-loop, braking is automatically determined by the feedback conditions and applied when needed. When operating open-loop modes, braking is only applied when the input signal is less than 50%. Open-loop mode (ERM and LRA) examples: 0% Input -> Negative full-scale output signal (braking) 25% Input -> Negative half-scale output signal (braking) 50% Input -> No output signal 75% Input -> Positive half-scale output signal 100% Input -> Positive full-scale output signal Closed-loop mode (ERM and LRA) examples: 0% to 50% Input -> No output signal 50% Input -> No output signal 75% Input -> Half-scale output signal 100% Input -> Full-scale output signal

pub fn set_bidir_input(&mut self, value: bool)

The BIDIR_INPUT bit selects how the engine interprets data. 0: Unidirectional input mode Braking is automatically determined by the feedback conditions and is applied when needed. Use of this mode also recovers an additional bit of vertical resolution. This mode should only be used for closed-loop operation. Examples:: 0% Input -> No output signal 50% Input -> Half-scale output signal 100% Input -> Full-scale output signal 1: Bidirectional input mode (default) This mode is compatible with traditional open-loop signaling and also works well with closed-loop mode. When operating closed-loop, braking is automatically determined by the feedback conditions and applied when needed. When operating open-loop modes, braking is only applied when the input signal is less than 50%. Open-loop mode (ERM and LRA) examples: 0% Input -> Negative full-scale output signal (braking) 25% Input -> Negative half-scale output signal (braking) 50% Input -> No output signal 75% Input -> Positive half-scale output signal 100% Input -> Positive full-scale output signal Closed-loop mode (ERM and LRA) examples: 0% to 50% Input -> No output signal 50% Input -> No output signal 75% Input -> Half-scale output signal 100% Input -> Full-scale output signal

pub fn brake_stabilizer(&self) -> bool

When this bit is set, loop gain is reduced when braking is almost complete to improve loop stability

pub fn set_brake_stabilizer(&mut self, value: bool)

When this bit is set, loop gain is reduced when braking is almost complete to improve loop stability

pub fn sample_time(&self) -> u8

LRA auto-resonance sampling time (Advanced use only) 0: 150 us 1: 200 us 2: 250 us 3: 300 us

pub fn set_sample_time(&mut self, value: u8)

LRA auto-resonance sampling time (Advanced use only) 0: 150 us 1: 200 us 2: 250 us 3: 300 us

pub fn blanking_time(&self) -> u8

Blanking time before the back-EMF AD makes a conversion. (Advanced use only)

pub fn set_blanking_time(&mut self, value: u8)

Blanking time before the back-EMF AD makes a conversion. (Advanced use only)

pub fn idiss_time(&self) -> u8

Current dissipation time. This bit is the time allowed for the current to dissipate from the actuator between PWM cycles for flyback mitigation. (Advanced use only)

pub fn set_idiss_time(&mut self, value: u8)

Current dissipation time. This bit is the time allowed for the current to dissipate from the actuator between PWM cycles for flyback mitigation. (Advanced use only)

Trait Implementations

impl<T> BitRange<T> for Control2Reg where     u8: BitRange<T>,

fn bit_range(&self, msb: usize, lsb: usize) -> T

Get a range of bits.

fn set_bit_range(&mut self, msb: usize, lsb: usize, value: T)

Set a range of bits.

impl Debug for Control2Reg

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.