Trait drone_cortexm::thr::ThrNvic[−][src]

pub trait ThrNvic: IntToken {
    fn enable_batch<F>(self, f: F)
    where
        F: FnOnce(&mut NvicIser<Self::NvicBlock>),
    { ... }

    fn enable(self, nvic_reg: &mut NvicIser<Self::NvicBlock>) { ... }

    fn enable_int(self) { ... }

    fn enabled(self) -> NvicIser<Self::NvicBlock> { ... }

    fn is_enabled(self, nvic_reg: &NvicIser<Self::NvicBlock>) -> bool { ... }

    fn is_int_enabled(self) -> bool { ... }

    fn disable_batch<F>(self, f: F)
    where
        F: FnOnce(&mut NvicIcer<Self::NvicBlock>),
    { ... }

    fn disable(self, nvic_reg: &mut NvicIcer<Self::NvicBlock>) { ... }

    fn disable_int(self) { ... }

    fn set_pending_batch<F>(self, f: F)
    where
        F: FnOnce(&mut NvicIspr<Self::NvicBlock>),
    { ... }

    fn set_pending(self, nvic_reg: &mut NvicIspr<Self::NvicBlock>) { ... }

    fn set_pending_int(self) { ... }

    fn clear_pending_batch<F>(self, f: F)
    where
        F: FnOnce(&mut NvicIcpr<Self::NvicBlock>),
    { ... }

    fn clear_pending(self, nvic_reg: &mut NvicIcpr<Self::NvicBlock>) { ... }

    fn clear_pending_int(self) { ... }

    fn pending(self) -> NvicIcpr<Self::NvicBlock> { ... }

    fn is_pending(self, nvic_reg: &NvicIcpr<Self::NvicBlock>) -> bool { ... }

    fn is_int_pending(self) -> bool { ... }

    fn active(self) -> NvicIabr<Self::NvicBlock> { ... }

    fn is_active(self, nvic_reg: &NvicIabr<Self::NvicBlock>) -> bool { ... }

    fn is_int_active(self) -> bool { ... }

    fn priority(self) -> u8 { ... }

    fn set_priority(self, priority: u8) { ... }
}

NVIC methods for interrupt tokens.

Provided methods

fn enable_batch<F>(self, f: F) where
    F: FnOnce(&mut NvicIser<Self::NvicBlock>), [src]

Enables multiple interrupts within the NVIC register.

fn enable(self, nvic_reg: &mut NvicIser<Self::NvicBlock>)[src]

Enables the interrupt.

fn enable_int(self)[src]

Enables the interrupt within the nvic_reg.

fn enabled(self) -> NvicIser<Self::NvicBlock>[src]

Returns the NVIC register of enabled states.

fn is_enabled(self, nvic_reg: &NvicIser<Self::NvicBlock>) -> bool[src]

Returns true if the interrupt is enabled.

fn is_int_enabled(self) -> bool[src]

Returns true if the interrupt is enabled within the nvic_reg.

fn disable_batch<F>(self, f: F) where
    F: FnOnce(&mut NvicIcer<Self::NvicBlock>), [src]

Disables multiple interrupts within the NVIC register.

fn disable(self, nvic_reg: &mut NvicIcer<Self::NvicBlock>)[src]

Disables the interrupt.

fn disable_int(self)[src]

Disables the interrupt within the nvic_reg.

fn set_pending_batch<F>(self, f: F) where
    F: FnOnce(&mut NvicIspr<Self::NvicBlock>), [src]

Sets multiple interrupts pending within the NVIC register.

fn set_pending(self, nvic_reg: &mut NvicIspr<Self::NvicBlock>)[src]

Sets the interrupt pending.

fn set_pending_int(self)[src]

Sets the interrupt pending within the nvic_reg.

fn clear_pending_batch<F>(self, f: F) where
    F: FnOnce(&mut NvicIcpr<Self::NvicBlock>), [src]

Clears multiple interrupts pending state within the NVIC register.

fn clear_pending(self, nvic_reg: &mut NvicIcpr<Self::NvicBlock>)[src]

Clears the interrupt pending state.

fn clear_pending_int(self)[src]

Clears the interrupt pending state within the nvic_reg.

fn pending(self) -> NvicIcpr<Self::NvicBlock>[src]

Returns the NVIC register of pending states.

fn is_pending(self, nvic_reg: &NvicIcpr<Self::NvicBlock>) -> bool[src]

Returns true if the interrupt is pending.

fn is_int_pending(self) -> bool[src]

Returns true if the interrupt is pending within the nvic_reg.

fn active(self) -> NvicIabr<Self::NvicBlock>[src]

Returns the NVIC register of active states.

fn is_active(self, nvic_reg: &NvicIabr<Self::NvicBlock>) -> bool[src]

Returns true if the interrupt is active.

fn is_int_active(self) -> bool[src]

Returns true if the interrupt is active within the nvic_reg.

fn priority(self) -> u8[src]

Reads the priority of the interrupt.

fn set_priority(self, priority: u8)[src]

Writes the priority of the interrupt.

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Implementors

impl<T: IntToken> ThrNvic for T[src]

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