Enum DmaCoherency 

pub enum DmaCoherency {
    Coherent,
    NonCoherent,
}

Cache-coherency relationship between one DMA device and the CPU.

This is a device property supplied by firmware or the platform bus. It is independent from address-mask and segment-layout constraints.

Variants

Coherent

CPU and device observe the same cacheable mapping without explicit cache maintenance.

NonCoherent

CPU ownership transitions require cache maintenance or a coherent CPU mapping supplied by the DMA backend.

Trait Implementations

impl Clone for DmaCoherency

fn clone(&self) -> DmaCoherency

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for DmaCoherency

impl Debug for DmaCoherency

fn fmt(&self, __derive_more_f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for DmaCoherency

impl Hash for DmaCoherency

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for DmaCoherency

fn eq(&self, other: &DmaCoherency) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for DmaCoherency