Enum Extension 

#[non_exhaustive]
pub enum Extension {
    E,
    M,
    A,
    F,
    D,
    Q,
    C,
    Zca,
    Zcf,
    Zcd,
    Zcmp,
    Zcmt,
    Zilsd,
    Zclsd,
    V,
    H,
    Zicsr,
    Zifencei,
    Zicond,
    Zalasr,
    Zacas,
    Zabha,
    Zawrs,
    Zicbom,
    Zicboz,
    Zicbop,
    Zihintntl,
    Zihintpause,
    Zimop,
    Zcmop,
    Zicfiss,
    Zicfilp,
    Zba,
    Zbb,
    Zbc,
    Zbs,
    Zbkb,
    Zbkc,
    Zbkx,
    Zknd,
    Zkne,
    Zknh,
    Zksed,
    Zksh,
    Zcb,
    Zfh,
    Zfhmin,
    Zfa,
    Zfbfmin,
    Zfinx,
    Zdinx,
    Zhinx,
    Zhinxmin,
    Zvfbfmin,
    Zvfbfwma,
    Zvbb,
    Zvbc,
    Zvkg,
    Zvkned,
    Zvknha,
    Zvknhb,
    Zvksed,
    Zvksh,
    Svinval,
    Sdext,
    Smrnmi,
    Ssctr,
    XTheadBa,
    XTheadBb,
    XTheadBs,
    XTheadCmo,
    XTheadCondMov,
    XTheadFMemIdx,
    XTheadFmv,
    XTheadInt,
    XTheadMac,
    XTheadMemIdx,
    XTheadMemPair,
    XTheadSync,
    XCValu,
    XCVbi,
    XCVbitmanip,
    XCVelw,
    XCVmac,
    XCVmem,
    XCVsimd,
}

A RISC-V extension that defines instructions disc-v can decode.

Extensions that define no instructions, such as Zkt or Sstc, are not listed; Decoder::from_march accepts and ignores them.

The instructions of the vector and vendor extensions are only decoded with the vector, vendor-thead and vendor-corev Cargo features, which are on by default.

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

E

The RV32E and RV64E bases: only registers x0-x15 exist, so instructions that use x16-x31 are reserved. This restricts the base ISA rather than adding instructions, so it is not in Extensions::DEFAULT.

M

Integer multiplication and division.

A

Atomic instructions.

F

Single-precision floating point.

D

Double-precision floating point. Implies F.

Q

Quad-precision floating point. Implies D.

C

Compressed instructions: Zca, and Zcf and Zcd when F and D are enabled.

Zca

Compressed integer instructions.

Zcf

Compressed single-precision loads and stores (RV32 only). Implies Zca and F.

Zcd

Compressed double-precision loads and stores. Implies Zca and D.

Zcmp

Compressed push, pop and register moves (cm.push, …). Implies Zca, and conflicts with Zcd.

Zcmt

Compressed table jumps (cm.jt, cm.jalt). Implies Zca and Zicsr, and conflicts with Zcd.

Zilsd

Load and store register pairs on RV32 (ld, sd).

Zclsd

Compressed load and store register pairs on RV32 (c.ld, c.sd, …). Implies Zilsd and Zca, and conflicts with Zcf.

V

Vectors.

H

The hypervisor extension.

Zicsr

Control and status register instructions.

Zifencei

fence.i.

Zicond

Integer conditional operations (czero.*).

Zalasr

Load-acquire and store-release (lw.aq, sw.rl, …).

Zacas

Atomic compare-and-swap (amocas.*). Implies A.

Zabha

Byte and halfword atomics (amoadd.b, …). Implies A.

Zawrs

Wait-on-reservation-set (wrs.*).

Zicbom

Cache-block management (cbo.clean, cbo.flush, cbo.inval).

Zicboz

Cache-block zero (cbo.zero).

Zicbop

Cache-block prefetch hints (prefetch.*).

Zihintntl

Non-temporal locality hints (ntl.*).

Zihintpause

The pause hint.

Zimop

May-be-operations (mop.r.N, mop.rr.N).

Zcmop

Compressed may-be-operations (c.mop.N). Implies C.

Zicfiss

Shadow stacks (sspush, sspopchk, ssrdp, ssamoswap.*). Implies Zimop.

Zicfilp

Landing pads (lpad).

Zba

Address generation (sh1add, …).

Zbb

Basic bit manipulation (andn, clz, …).

Zbc

Carry-less multiplication (clmul, …).

Zbs

Single-bit instructions (bset, …).

Zbkb

Bit manipulation for cryptography (pack, brev8, …). It also provides several Zbb instructions, such as rol and rev8.

Zbkc

Carry-less multiplication for cryptography: Zbc’s clmul and clmulh.

Zbkx

Crossbar permutations (xperm4, xperm8).

Zknd

AES decryption.

Zkne

AES encryption.

Zknh

SHA-256 and SHA-512.

Zksed

SM4.

Zksh

SM3.

Zcb

Simple compressed instructions (c.lbu, c.mul, …). Implies C.

Zfh

Half-precision floating point. Implies Zfhmin.

Zfhmin

Minimal half-precision floating point: loads, stores and conversions. Implies F.

Zfa

Additional floating-point instructions (fli, fround, …). Implies F.

Zfbfmin

Conversions between BFloat16 and single precision. Implies F.

Zfinx

Single-precision floating point in the integer registers: F’s instructions except its loads, stores and moves, with integer register operands. Conflicts with F (and so with the extensions that imply it, such as D, Zfa and C’s Zcf).

Zdinx

Double-precision floating point in the integer registers (register pairs on RV32). Implies Zfinx.

Zhinx

Half-precision floating point in the integer registers. Implies Zhinxmin.

Zhinxmin

Minimal half-precision floating point in the integer registers: the conversions. Implies Zfinx.

Zvfbfmin

Vector BFloat16 conversions. Implies V.

Zvfbfwma

Vector BFloat16 widening multiply-add. Implies Zvfbfmin.

Zvbb

Vector bit manipulation. Implies V.

Zvbc

Vector carry-less multiplication. Implies V.

Zvkg

Vector GCM/GMAC. Implies V.

Zvkned

Vector AES. Implies V.

Zvknha

Vector SHA-256. Implies V.

Zvknhb

Vector SHA-256 and SHA-512. Implies Zvknha, whose instructions it shares.

Zvksed

Vector SM4. Implies V.

Zvksh

Vector SM3. Implies V.

Svinval

Fine-grained address-translation cache invalidation (sinval.vma, …).

Sdext

Debug mode (dret).

Smrnmi

Resumable non-maskable interrupts (mnret).

Ssctr

Control-transfer records (sctrclr).

XTheadBa

T-Head address calculation (th.addsl).

XTheadBb

T-Head basic bit manipulation (th.ext, th.ff1, th.rev, …).

XTheadBs

T-Head single-bit test (th.tst).

XTheadCmo

T-Head cache management (th.dcache.*, th.icache.*, th.l2cache.*).

XTheadCondMov

T-Head conditional moves (th.mveqz, th.mvnez).

XTheadFMemIdx

T-Head indexed floating-point loads and stores (th.flrw, …). Implies F.

XTheadFmv

T-Head moves of the upper half of a double-precision register on RV32 (th.fmv.hw.x, th.fmv.x.hw). Implies D.

XTheadInt

T-Head interrupt register saving (th.ipush, th.ipop).

XTheadMac

T-Head multiply-accumulate (th.mula, …).

XTheadMemIdx

T-Head indexed loads and stores, and loads and stores that update the base register (th.lrw, th.lbia, …).

XTheadMemPair

T-Head load and store pairs (th.lwd, th.sdd, …).

XTheadSync

T-Head synchronization (th.sync, th.sfence.vmas, …).

XCValu

CORE-V ALU operations (cv.abs, cv.clip, cv.addn, …).

XCVbi

CORE-V branches with an immediate (cv.beqimm, cv.bneimm).

XCVbitmanip

CORE-V bit manipulation (cv.extract, cv.bset, cv.cnt, …).

XCVelw

CORE-V event load (cv.elw).

XCVmac

CORE-V multiply-accumulate (cv.mac, cv.mulsn, …).

XCVmem

CORE-V post-increment and register-offset loads and stores (cv.lw, cv.sw, …).

XCVsimd

CORE-V packed SIMD (cv.add.h, cv.dotsp.b, …).

Implementations

impl Extension

pub const fn name(self) -> &'static str

The extension’s name in an ISA string, such as "zba" or "m".

impl Extension

pub fn from_name(name: &str) -> Option<Extension>

The extension named name in an ISA string, ignoring case.

Trait Implementations

impl Clone for Extension

fn clone(&self) -> Self

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Extension

impl Debug for Extension

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Display for Extension

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for Extension

impl From<Extension> for Extensions

fn from(ext: Extension) -> Self

Converts to this type from the input type.

impl FromIterator<Extension> for Extensions

fn from_iter<I: IntoIterator<Item = Extension>>(iter: I) -> Self

Creates a value from an iterator.

impl Hash for Extension

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl Ord for Extension

fn cmp(&self, other: &Self) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Self

where Self: Sized,

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Self

where Self: Sized,

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Self

where Self: Sized,

Restrict a value to a certain interval.

fn clamp_to<R>(self, range: R) -> Self

where Self: Sized, R: ClampBounds<Self>,

🔬This is a nightly-only experimental API. (clamp_to)

Restrict a value to a certain range.

impl PartialEq for Extension

fn eq(&self, other: &Self) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl PartialOrd for Extension

fn partial_cmp(&self, other: &Self) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

Tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

Tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

Tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

Tests greater than or equal to (for self and other) and is used by the >= operator.

impl StructuralPartialEq for Extension