pub type TimerCtrlReg = RegValueT<TimerCtrlReg_SPEC>;Expand description
Timer control register
Aliased Type§
pub struct TimerCtrlReg { /* private fields */ }Implementations§
Source§impl TimerCtrlReg
impl TimerCtrlReg
Sourcepub fn tim_cap_gpio4_irq_en(
self,
) -> RegisterFieldBool<14, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_cap_gpio4_irq_en( self, ) -> RegisterFieldBool<14, 1, 0, TimerCtrlReg_SPEC, RW>
0 = Event on GPIO4 does not create a CAPTIM interrrupt 1 = Event on GPIO4 creates a CAPTIM interrrupt
Sourcepub fn tim_cap_gpio3_irq_en(
self,
) -> RegisterFieldBool<13, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_cap_gpio3_irq_en( self, ) -> RegisterFieldBool<13, 1, 0, TimerCtrlReg_SPEC, RW>
0 = Event on GPIO3 does not create a CAPTIM interrrupt 1 = Event on GPIO3 creates a CAPTIM interrrupt
Sourcepub fn tim_cap_gpio2_irq_en(
self,
) -> RegisterFieldBool<12, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_cap_gpio2_irq_en( self, ) -> RegisterFieldBool<12, 1, 0, TimerCtrlReg_SPEC, RW>
0 = Event on GPIO2 does not create a CAPTIM interrrupt 1 = Event on GPIO2 creates a CAPTIM interrrupt
Sourcepub fn tim_cap_gpio1_irq_en(
self,
) -> RegisterFieldBool<11, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_cap_gpio1_irq_en( self, ) -> RegisterFieldBool<11, 1, 0, TimerCtrlReg_SPEC, RW>
0 = Event on GPIO1 does not create a CAPTIM interrrupt 1 = Event on GPIO1 creates a CAPTIM interrrupt
Sourcepub fn tim_in4_event_fall_en(
self,
) -> RegisterFieldBool<10, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_in4_event_fall_en( self, ) -> RegisterFieldBool<10, 1, 0, TimerCtrlReg_SPEC, RW>
Event input 4 edge type 1 = falling edge 0 = rising edge
Sourcepub fn tim_in3_event_fall_en(
self,
) -> RegisterFieldBool<9, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_in3_event_fall_en( self, ) -> RegisterFieldBool<9, 1, 0, TimerCtrlReg_SPEC, RW>
Event input 3 edge type 1 = falling edge 0 = rising edge
Sourcepub fn tim_clk_en(self) -> RegisterFieldBool<8, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_clk_en(self) -> RegisterFieldBool<8, 1, 0, TimerCtrlReg_SPEC, RW>
Timer clock enable 1 = clock enabled 0 = clock disabled
Sourcepub fn tim_sys_clk_en(self) -> RegisterFieldBool<7, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_sys_clk_en(self) -> RegisterFieldBool<7, 1, 0, TimerCtrlReg_SPEC, RW>
Select clock 1 = Timer uses the DIVN clock 0 = Timer uses the lp clock
Sourcepub fn tim_free_run_mode_en(
self,
) -> RegisterFieldBool<6, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_free_run_mode_en( self, ) -> RegisterFieldBool<6, 1, 0, TimerCtrlReg_SPEC, RW>
Valid when timer counts up, if it is ‘1’ timer does not zero when reaches to reload value. it becomes zero only when it reaches the max value.
Sourcepub fn tim_irq_en(self) -> RegisterFieldBool<5, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_irq_en(self) -> RegisterFieldBool<5, 1, 0, TimerCtrlReg_SPEC, RW>
Interrupt mask 1 = timer IRQ is unmasked 0 = timer IRQ is masked
Sourcepub fn tim_in2_event_fall_en(
self,
) -> RegisterFieldBool<4, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_in2_event_fall_en( self, ) -> RegisterFieldBool<4, 1, 0, TimerCtrlReg_SPEC, RW>
Event input 2 edge type 1 = falling edge 0 = rising edge
Sourcepub fn tim_in1_event_fall_en(
self,
) -> RegisterFieldBool<3, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_in1_event_fall_en( self, ) -> RegisterFieldBool<3, 1, 0, TimerCtrlReg_SPEC, RW>
Event input 1 edge type 1 = falling edge 0 = rising edge
Sourcepub fn tim_count_down_en(
self,
) -> RegisterFieldBool<2, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_count_down_en( self, ) -> RegisterFieldBool<2, 1, 0, TimerCtrlReg_SPEC, RW>
Timer count direction 1 = down 0 = up
Sourcepub fn tim_oneshot_mode_en(
self,
) -> RegisterFieldBool<1, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_oneshot_mode_en( self, ) -> RegisterFieldBool<1, 1, 0, TimerCtrlReg_SPEC, RW>
Timer mode 1 = One shot enabled 0 = Counter enabled
Sourcepub fn tim_en(self) -> RegisterFieldBool<0, 1, 0, TimerCtrlReg_SPEC, RW>
pub fn tim_en(self) -> RegisterFieldBool<0, 1, 0, TimerCtrlReg_SPEC, RW>
Timer enable 1 = On 0 = Off