Type Alias CacheCtrl2Reg 

pub type CacheCtrl2Reg = RegValueT<CacheCtrl2Reg_SPEC>;

Cache control register 2

Aliased Type

pub struct CacheCtrl2Reg { /* private fields */ }

Implementations

impl CacheCtrl2Reg

pub fn cache_cgen(self) -> RegisterFieldBool<10, 1, 0, CacheCtrl2Reg_SPEC, RW>

0: Cache controller clock gating is not enabled. 1: Cache controller clock gating is enabled (enabling power saving). Note: This bit must be set to ‘0’ (default) when setting the CACHE_FLUSH bit while executing from other than QSPI FLASH cached, e.g. from Booter or SYSRAM.

pub fn cache_wen(self) -> RegisterFieldBool<9, 1, 0, CacheCtrl2Reg_SPEC, RW>

0: Cache Data and TAG memory read only. 1: Cache Data and TAG memory read/write. The TAG and Data memory are only updated by the cache controller. There is no HW protection to prevent unauthorized access by the ARM. Note: When accessing the memory mapped Cache Data and TAG memory (for debugging purposes) only 32 bits access is allowed to the Cache Data memory and only 16 bits access is allowed to the Cache TAG memory.

pub fn cache_len( self, ) -> RegisterField<0, 0x1ff, 1, 0, u16, u16, CacheCtrl2Reg_SPEC, RW>

Length of QSPI FLASH cacheable memory. N*64 KByte. N = 0 to 512 (max. of 32 Mbyte). Setting CACHE_LEN=0 disables the cache. Note 1: The max. relevant CACHE_LEN setting depends on the chosen Flash region (program) size. Note 2: The first block (CACHE_LEN=1) includes the memory space specified by CACHE_FLASH_REG[FLASH_REGION_OFFSET].

Trait Implementations

impl Default for CacheCtrl2Reg

fn default() -> CacheCtrl2Reg

Returns the “default value” for a type.