pub type CacheMrmCtrlReg = RegValueT<CacheMrmCtrlReg_SPEC>;Expand description
Cache MRM (Miss Rate Monitor) CONTROL register
Aliased Type§
pub struct CacheMrmCtrlReg { /* private fields */ }Implementations§
Source§impl CacheMrmCtrlReg
impl CacheMrmCtrlReg
Sourcepub fn mrm_irq_thres_status(
self,
) -> RegisterFieldBool<3, 1, 0, CacheMrmCtrlReg_SPEC, RW>
pub fn mrm_irq_thres_status( self, ) -> RegisterFieldBool<3, 1, 0, CacheMrmCtrlReg_SPEC, RW>
0: No interrupt is generated. 1: Interrupt (pulse-sensitive) is generated because the number of cache misses reached the programmed threshold (threshold != 0).
Sourcepub fn mrm_irq_tint_status(
self,
) -> RegisterFieldBool<2, 1, 0, CacheMrmCtrlReg_SPEC, RW>
pub fn mrm_irq_tint_status( self, ) -> RegisterFieldBool<2, 1, 0, CacheMrmCtrlReg_SPEC, RW>
0: No interrupt is generated. 1: Interrupt (pulse-sensitive) is generated because the time interval counter reached the end (time interval != 0).
Sourcepub fn mrm_irq_mask(
self,
) -> RegisterFieldBool<1, 1, 0, CacheMrmCtrlReg_SPEC, RW>
pub fn mrm_irq_mask( self, ) -> RegisterFieldBool<1, 1, 0, CacheMrmCtrlReg_SPEC, RW>
0: Disables interrupt generation. 1: Enables interrupt generation. Note: The Cache MRM generates a pulse-sensitive interrupt towards the ARM processor,
Sourcepub fn mrm_start(self) -> RegisterFieldBool<0, 1, 0, CacheMrmCtrlReg_SPEC, RW>
pub fn mrm_start(self) -> RegisterFieldBool<0, 1, 0, CacheMrmCtrlReg_SPEC, RW>
0: Freeze the “misses/hits” counters and reset the time interval counter to the programmed value in CACHE_MRM_TINT_REG. 1: Enables the counters. Note: In case CACHE_MRM_CTRL_REG[MRM_START] is set to ‘1’ and CACHE_MRM_TINT_REG (!=0) is used for the MRM interrupt generation, the time interval counter counts down (on a fixed reference clock of 16 MHz) until it’s ‘0’. At that time CACHE_MRM_CTRL_REG[MRM_START] will be reset automatically to ‘0’ by the MRM hardware and the MRM interrupt will be generated.