Type Alias CacheCtrl1Reg 

pub type CacheCtrl1Reg = RegValueT<CacheCtrl1Reg_SPEC>;

Cache control register 1

Aliased Type

pub struct CacheCtrl1Reg { /* private fields */ }

Implementations

impl CacheCtrl1Reg

pub fn cache_res1(self) -> RegisterFieldBool<1, 1, 0, CacheCtrl1Reg_SPEC, RW>

Reserved. Always keep 0.

pub fn cache_flush(self) -> RegisterFieldBool<0, 1, 0, CacheCtrl1Reg_SPEC, W>

Writing a ‘1’ into this bit, flushes the contents of the tag memories which invalidates the content of the cache memory. The read of this bit is always ‘0’. Note: The flushing of the cache TAG memory takes 0x100 or 0x200 HCLK cycles for a Cache Data RAM size of 8 KB resp. 16 KB.

Trait Implementations

impl Default for CacheCtrl1Reg

fn default() -> CacheCtrl1Reg

Returns the “default value” for a type.